From 51ff8f742a9b554a5ff2725f7ed393c7c6311414bf7bba7fe787cf2fee45c7e7 Mon Sep 17 00:00:00 2001 From: Michael Matz Date: Mon, 12 Aug 2024 14:15:41 +0000 Subject: [PATCH] Nicer changelog. OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=473 --- binutils.changes | 86 +++++++++++++++++++++++++----------------------- 1 file changed, 45 insertions(+), 41 deletions(-) diff --git a/binutils.changes b/binutils.changes index 8242c76..53b0824 100644 --- a/binutils.changes +++ b/binutils.changes @@ -2,47 +2,51 @@ Tue Aug 6 14:09:24 UTC 2024 - Michael Matz - Update to version 2.43: -* new .base64 pseudo-op, allowing base64 encoded data as strings -* Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF - (APX_F now fully supported) -* x86 Intel syntax now warns about more mnemonic suffixes -* macros and .irp/.irpc/.rept bodies can use \+ to get at number of times - the macro/body was executed -* aarch64: support 'armv9.5-a' for -march, add support for LUT and LUT2 -* s390: base register operand in D(X,B) and D(L,B) can now be omitted - (ala 'D(X,)'); warn when register type doesn't match operand type - (use option 'warn-regtype-mismatch=[strict|relaxed|no]' to adjust) -* riscv: support various extensions: Zacas, Zcmp, Zfbfmin, Zvfbfmin, - Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw, XSfCease, all at - version 1.0; - remove support for assembly of privileged spec 1.9.1 (linking support - remains) -* arm: remove support for some old co-processors: Maverick and FPA -* mips: '--trap' now causes either trap or breakpoint instructions to - be emitted as per current ISA, instead of always using trap insn - and failing when current ISA was incompatible with that -* LoongArch: accept .option pseudo-op for fine-grained control - of assembly code options; add support for DT_RELR -* readelf: now displays RELR relocations in full detail; - add -j/--display-section to show just those section(s) content - according to their type -* objdump/readelf now dump also .eh_frame_hdr (when present) when - dumping .eh_frame -* gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake processors; - add minimal support for riscv -* linker: - - put .got and .got.plt into relro segment - - add -z isa-level-report=[none|all|needed|used] to the x86 ELF - linker to report needed and used x86-64 ISA levels - - add --rosegment option which changes the -z separate-code option - so that only one read-only segment is created (instead of two) - - add --section-ordering-file option to add extra mapping - of input sections to output sections - - add -plugin-save-temps to store plugin intermediate files permanently -* Removed binutils-2.42.tar.bz2, binutils-2.42-branch.diff.gz. -* Added binutils-2.43.tar.bz2, binutils-2.43-branch.diff.gz. -* Removed upstream patch riscv-no-relax.patch. -* Rebased ld-relro.diff and binutils-revert-rela.diff. + * new .base64 pseudo-op, allowing base64 encoded data as strings + * Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF + (APX_F now fully supported) + * x86 Intel syntax now warns about more mnemonic suffixes + * macros and .irp/.irpc/.rept bodies can use \+ to get at number + of times the macro/body was executed + * aarch64: support 'armv9.5-a' for -march, add support for LUT + and LUT2 + * s390: base register operand in D(X,B) and D(L,B) can now be + omitted (ala 'D(X,)'); warn when register type doesn't match + operand type (use option + 'warn-regtype-mismatch=[strict|relaxed|no]' to adjust) + * riscv: support various extensions: Zacas, Zcmp, Zfbfmin, + Zvfbfmin, Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw, + XSfCease, all at version 1.0; + remove support for assembly of privileged spec 1.9.1 (linking + support remains) + * arm: remove support for some old co-processors: Maverick and FPA + * mips: '--trap' now causes either trap or breakpoint instructions + to be emitted as per current ISA, instead of always using trap + insn and failing when current ISA was incompatible with that + * LoongArch: accept .option pseudo-op for fine-grained control + of assembly code options; add support for DT_RELR + * readelf: now displays RELR relocations in full detail; + add -j/--display-section to show just those section(s) content + according to their type + * objdump/readelf now dump also .eh_frame_hdr (when present) when + dumping .eh_frame + * gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake + processors; add minimal support for riscv + * linker: + - put .got and .got.plt into relro segment + - add -z isa-level-report=[none|all|needed|used] to the x86 ELF + linker to report needed and used x86-64 ISA levels + - add --rosegment option which changes the -z separate-code + option so that only one read-only segment is created (instead + of two) + - add --section-ordering-file option to add extra + mapping of input sections to output sections + - add -plugin-save-temps to store plugin intermediate files + permanently +- Removed binutils-2.42.tar.bz2, binutils-2.42-branch.diff.gz. +- Added binutils-2.43.tar.bz2, binutils-2.43-branch.diff.gz. +- Removed upstream patch riscv-no-relax.patch. +- Rebased ld-relro.diff and binutils-revert-rela.diff. ------------------------------------------------------------------- Thu Jun 13 08:35:38 UTC 2024 - Andreas Schwab