diff --git a/binutils.changes b/binutils.changes index 3f87849..2d8d119 100644 --- a/binutils.changes +++ b/binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/binutils.spec b/binutils.spec index f33e28e..7d2d814 100644 --- a/binutils.spec +++ b/binutils.spec @@ -61,7 +61,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-aarch64-binutils.changes b/cross-aarch64-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-aarch64-binutils.changes +++ b/cross-aarch64-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-aarch64-binutils.spec b/cross-aarch64-binutils.spec index bb77371..9f8349a 100644 --- a/cross-aarch64-binutils.spec +++ b/cross-aarch64-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-arm-binutils.changes b/cross-arm-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-arm-binutils.changes +++ b/cross-arm-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-arm-binutils.spec b/cross-arm-binutils.spec index 7352357..9fd4ae1 100644 --- a/cross-arm-binutils.spec +++ b/cross-arm-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-avr-binutils.changes b/cross-avr-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-avr-binutils.changes +++ b/cross-avr-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-avr-binutils.spec b/cross-avr-binutils.spec index 1480e3e..6211420 100644 --- a/cross-avr-binutils.spec +++ b/cross-avr-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-epiphany-binutils.changes b/cross-epiphany-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-epiphany-binutils.changes +++ b/cross-epiphany-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-epiphany-binutils.spec b/cross-epiphany-binutils.spec index 4427ee1..e9a8201 100644 --- a/cross-epiphany-binutils.spec +++ b/cross-epiphany-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-hppa-binutils.changes b/cross-hppa-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-hppa-binutils.changes +++ b/cross-hppa-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-hppa-binutils.spec b/cross-hppa-binutils.spec index 77a1378..55cf6b4 100644 --- a/cross-hppa-binutils.spec +++ b/cross-hppa-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-hppa64-binutils.changes b/cross-hppa64-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-hppa64-binutils.changes +++ b/cross-hppa64-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-hppa64-binutils.spec b/cross-hppa64-binutils.spec index f94051d..1bb5d35 100644 --- a/cross-hppa64-binutils.spec +++ b/cross-hppa64-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-i386-binutils.changes b/cross-i386-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-i386-binutils.changes +++ b/cross-i386-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-i386-binutils.spec b/cross-i386-binutils.spec index c284259..4b76342 100644 --- a/cross-i386-binutils.spec +++ b/cross-i386-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-ia64-binutils.changes b/cross-ia64-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-ia64-binutils.changes +++ b/cross-ia64-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-ia64-binutils.spec b/cross-ia64-binutils.spec index 18aea03..417f3b0 100644 --- a/cross-ia64-binutils.spec +++ b/cross-ia64-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-m68k-binutils.changes b/cross-m68k-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-m68k-binutils.changes +++ b/cross-m68k-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-m68k-binutils.spec b/cross-m68k-binutils.spec index c23bf38..da72b3b 100644 --- a/cross-m68k-binutils.spec +++ b/cross-m68k-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-mips-binutils.changes b/cross-mips-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-mips-binutils.changes +++ b/cross-mips-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-mips-binutils.spec b/cross-mips-binutils.spec index 89a0314..a598434 100644 --- a/cross-mips-binutils.spec +++ b/cross-mips-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-ppc-binutils.changes b/cross-ppc-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-ppc-binutils.changes +++ b/cross-ppc-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-ppc-binutils.spec b/cross-ppc-binutils.spec index 534a4df..94693ff 100644 --- a/cross-ppc-binutils.spec +++ b/cross-ppc-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-ppc64-binutils.changes b/cross-ppc64-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-ppc64-binutils.changes +++ b/cross-ppc64-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-ppc64-binutils.spec b/cross-ppc64-binutils.spec index efcce6e..a0deb15 100644 --- a/cross-ppc64-binutils.spec +++ b/cross-ppc64-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-ppc64le-binutils.changes b/cross-ppc64le-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-ppc64le-binutils.changes +++ b/cross-ppc64le-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-ppc64le-binutils.spec b/cross-ppc64le-binutils.spec index 9ecc55f..fdc0f60 100644 --- a/cross-ppc64le-binutils.spec +++ b/cross-ppc64le-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-riscv64-binutils.changes b/cross-riscv64-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-riscv64-binutils.changes +++ b/cross-riscv64-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-riscv64-binutils.spec b/cross-riscv64-binutils.spec index 2551aff..41e0e79 100644 --- a/cross-riscv64-binutils.spec +++ b/cross-riscv64-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-rx-binutils.changes b/cross-rx-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-rx-binutils.changes +++ b/cross-rx-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-rx-binutils.spec b/cross-rx-binutils.spec index 882bab8..3de3e26 100644 --- a/cross-rx-binutils.spec +++ b/cross-rx-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-s390-binutils.changes b/cross-s390-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-s390-binutils.changes +++ b/cross-s390-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-s390-binutils.spec b/cross-s390-binutils.spec index 3908df9..2a125c8 100644 --- a/cross-s390-binutils.spec +++ b/cross-s390-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-s390x-binutils.changes b/cross-s390x-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-s390x-binutils.changes +++ b/cross-s390x-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-s390x-binutils.spec b/cross-s390x-binutils.spec index 2184463..5fa7a90 100644 --- a/cross-s390x-binutils.spec +++ b/cross-s390x-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-sparc-binutils.changes b/cross-sparc-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-sparc-binutils.changes +++ b/cross-sparc-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-sparc-binutils.spec b/cross-sparc-binutils.spec index 0ca30cd..10d702e 100644 --- a/cross-sparc-binutils.spec +++ b/cross-sparc-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-sparc64-binutils.changes b/cross-sparc64-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-sparc64-binutils.changes +++ b/cross-sparc64-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-sparc64-binutils.spec b/cross-sparc64-binutils.spec index 972723b..dcef4ef 100644 --- a/cross-sparc64-binutils.spec +++ b/cross-sparc64-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-spu-binutils.changes b/cross-spu-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-spu-binutils.changes +++ b/cross-spu-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-spu-binutils.spec b/cross-spu-binutils.spec index 74f1ba2..e5020ea 100644 --- a/cross-spu-binutils.spec +++ b/cross-spu-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-x86_64-binutils.changes b/cross-x86_64-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-x86_64-binutils.changes +++ b/cross-x86_64-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-x86_64-binutils.spec b/cross-x86_64-binutils.spec index 5aff2d6..8f71d15 100644 --- a/cross-x86_64-binutils.spec +++ b/cross-x86_64-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # # diff --git a/cross-xtensa-binutils.changes b/cross-xtensa-binutils.changes index 3f87849..2d8d119 100644 --- a/cross-xtensa-binutils.changes +++ b/cross-xtensa-binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Wed Oct 2 12:20:41 UTC 2019 - matz@suse.com + +- Add avr, epiphany and rx to target_list so that the common + binutils can handle all objects we can create with crosses. + [bsc#1152590] + ------------------------------------------------------------------- Mon Sep 9 17:19:56 UTC 2019 - matz@suse.com diff --git a/cross-xtensa-binutils.spec b/cross-xtensa-binutils.spec index 730a167..3098d8f 100644 --- a/cross-xtensa-binutils.spec +++ b/cross-xtensa-binutils.spec @@ -64,7 +64,7 @@ Release: 0 %else %define build_multitarget 0 %endif -%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64 xtensa +%define target_list aarch64 alpha armv5l armv6l armv7l armv8l avr epiphany hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 rx s390 s390x sh4 sparc sparc64 x86_64 xtensa # # #