forked from pool/binutils
f32da6f20f
* new .base64 pseudo-op, allowing base64 encoded data as strings * Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF (APX_F now fully supported) * x86 Intel syntax now warns about more mnemonic suffixes * macros and .irp/.irpc/.rept bodies can use \+ to get at number of times the macro/body was executed * aarch64: support 'armv9.5-a' for -march, add support for LUT and LUT2 * s390: base register operand in D(X,B) and D(L,B) can now be omitted (ala 'D(X,)'); warn when register type doesn't match operand type (use option 'warn-regtype-mismatch=[strict|relaxed|no]' to adjust) * riscv: support various extensions: Zacas, Zcmp, Zfbfmin, Zvfbfmin, Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw, XSfCease, all at version 1.0; remove support for assembly of privileged spec 1.9.1 (linking support remains) * arm: remove support for some old co-processors: Maverick and FPA * mips: '--trap' now causes either trap or breakpoint instructions to be emitted as per current ISA, instead of always using trap insn and failing when current ISA was incompatible with that * LoongArch: accept .option pseudo-op for fine-grained control of assembly code options; add support for DT_RELR * readelf: now displays RELR relocations in full detail; add -j/--display-section to show just those section(s) content according to their type * objdump/readelf now dump also .eh_frame_hdr (when present) when dumping .eh_frame * gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake processors; add minimal support for riscv * linker: OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=471
26 lines
1.1 KiB
Diff
26 lines
1.1 KiB
Diff
Index: binutils-2.42/gas/config/tc-i386.c
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===================================================================
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--- binutils-2.42.orig/gas/config/tc-i386.c 2024-01-29 01:00:00.000000000 +0100
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+++ binutils-2.42/gas/config/tc-i386.c 2024-02-05 17:54:33.515139672 +0100
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@@ -2992,13 +2992,17 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED
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{
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check_cpu_arch_compatible (string, cpu_arch[j].enable);
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+ /* XXX code in the wild calls 'as --64' (to generate ELF64),
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+ but then does '.arch i386' first and only then '.code32' or
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+ '.code16'. This checking here would require swapping these
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+ two directives, so just warn for the time being. */
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if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 )
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{
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- as_bad (_("64bit mode not supported on `%s'."),
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+ as_warn (_("64bit mode not supported on `%s' (consider swapping .arch and .code directives)."),
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cpu_arch[j].name);
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- (void) restore_line_pointer (e);
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+ /*(void) restore_line_pointer (e);
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ignore_rest_of_line ();
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- return;
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+ return;*/
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}
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if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386)
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