SHA256
1
0
forked from pool/cpupower
cpupower/turbostat_decode_MSR_IA32_MISC_ENABLE_only_on_Intel.patch

15 lines
478 B
Diff

Index: turbostat-17.04.12/turbostat.c
===================================================================
--- turbostat-17.04.12.orig/turbostat.c
+++ turbostat-17.04.12/turbostat.c
@@ -3895,6 +3895,9 @@ void decode_misc_enable_msr(void)
{
unsigned long long msr;
+ if (!genuine_intel)
+ return;
+
if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
base_cpu, msr,