forked from pool/glibc
Accepting request 1105262 from home:Andreas_Schwab:Factory
- Require that elf/check-localplt does not fail - glibc-2.3.90-langpackdir.diff: add hidden alias for __strcpy_chk - cache-amd-legacy.patch: x86: Fix for cache computation on AMD legacy cpus - cache-intel-shared.patch: x86: Fix incorrect scope of setting `shared_per_thread` (BZ# 30745) OBS-URL: https://build.opensuse.org/request/show/1105262 OBS-URL: https://build.opensuse.org/package/show/Base:System/glibc?expand=0&rev=659
This commit is contained in:
Git OBS Bridge
parent
f252c599f1
commit
621320af4e
286
cache-amd-legacy.patch
Normal file
286
cache-amd-legacy.patch
Normal file
@ -0,0 +1,286 @@
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From ced101ed9d3b7cfd12d97ef24940cb00b8658c81 Mon Sep 17 00:00:00 2001
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From: Sajan Karumanchi <sajan.karumanchi@amd.com>
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Date: Tue, 1 Aug 2023 15:20:55 +0000
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Subject: [PATCH] x86: Fix for cache computation on AMD legacy cpus.
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Some legacy AMD CPUs and hypervisors have the _cpuid_ '0x8000_001D'
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set to Zero, thus resulting in zeroed-out computed cache values.
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This patch reintroduces the old way of cache computation as a
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fail-safe option to handle these exceptions.
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Fixed 'level4_cache_size' value through handle_amd().
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Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>
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Tested-by: Florian Weimer <fweimer@redhat.com>
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---
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sysdeps/x86/dl-cacheinfo.h | 226 ++++++++++++++++++++++++++++++++-----
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1 file changed, 199 insertions(+), 27 deletions(-)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index cd4d0351ae..285773039f 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -315,40 +315,206 @@ handle_amd (int name)
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{
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unsigned int eax;
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unsigned int ebx;
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- unsigned int ecx;
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+ unsigned int ecx = 0;
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unsigned int edx;
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- unsigned int count = 0x1;
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+ unsigned int max_cpuid = 0;
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+ unsigned int fn = 0;
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/* No level 4 cache (yet). */
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if (name > _SC_LEVEL3_CACHE_LINESIZE)
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return 0;
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- if (name >= _SC_LEVEL3_CACHE_SIZE)
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- count = 0x3;
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- else if (name >= _SC_LEVEL2_CACHE_SIZE)
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- count = 0x2;
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- else if (name >= _SC_LEVEL1_DCACHE_SIZE)
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- count = 0x0;
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+ __cpuid (0x80000000, max_cpuid, ebx, ecx, edx);
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+
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+ if (max_cpuid >= 0x8000001D)
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+ /* Use __cpuid__ '0x8000_001D' to compute cache details. */
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+ {
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+ unsigned int count = 0x1;
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+
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+ if (name >= _SC_LEVEL3_CACHE_SIZE)
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+ count = 0x3;
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+ else if (name >= _SC_LEVEL2_CACHE_SIZE)
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+ count = 0x2;
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+ else if (name >= _SC_LEVEL1_DCACHE_SIZE)
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+ count = 0x0;
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+
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+ __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);
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+
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+ if (ecx != 0)
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+ {
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+ switch (name)
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+ {
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+ case _SC_LEVEL1_ICACHE_ASSOC:
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+ case _SC_LEVEL1_DCACHE_ASSOC:
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+ case _SC_LEVEL2_CACHE_ASSOC:
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+ case _SC_LEVEL3_CACHE_ASSOC:
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+ return ((ebx >> 22) & 0x3ff) + 1;
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+ case _SC_LEVEL1_ICACHE_LINESIZE:
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+ case _SC_LEVEL1_DCACHE_LINESIZE:
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+ case _SC_LEVEL2_CACHE_LINESIZE:
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+ case _SC_LEVEL3_CACHE_LINESIZE:
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+ return (ebx & 0xfff) + 1;
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+ case _SC_LEVEL1_ICACHE_SIZE:
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+ case _SC_LEVEL1_DCACHE_SIZE:
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+ case _SC_LEVEL2_CACHE_SIZE:
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+ case _SC_LEVEL3_CACHE_SIZE:
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+ return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1);
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+ default:
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+ __builtin_unreachable ();
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+ }
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+ return -1;
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+ }
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+ }
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+
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+ /* Legacy cache computation for CPUs prior to Bulldozer family.
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+ This is also a fail-safe mechanism for some hypervisors that
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+ accidentally configure __cpuid__ '0x8000_001D' to Zero. */
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- __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);
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+ fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
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+
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+ if (max_cpuid < fn)
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+ return 0;
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+
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+ __cpuid (fn, eax, ebx, ecx, edx);
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+
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+ if (name < _SC_LEVEL1_DCACHE_SIZE)
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+ {
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+ name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
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+ ecx = edx;
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+ }
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switch (name)
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{
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- case _SC_LEVEL1_ICACHE_ASSOC:
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- case _SC_LEVEL1_DCACHE_ASSOC:
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- case _SC_LEVEL2_CACHE_ASSOC:
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+ case _SC_LEVEL1_DCACHE_SIZE:
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+ return (ecx >> 14) & 0x3fc00;
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+
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+ case _SC_LEVEL1_DCACHE_ASSOC:
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+ ecx >>= 16;
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+ if ((ecx & 0xff) == 0xff)
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+ {
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+ /* Fully associative. */
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+ return (ecx << 2) & 0x3fc00;
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+ }
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+ return ecx & 0xff;
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+
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+ case _SC_LEVEL1_DCACHE_LINESIZE:
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+ return ecx & 0xff;
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+
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+ case _SC_LEVEL2_CACHE_SIZE:
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+ return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
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+
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+ case _SC_LEVEL2_CACHE_ASSOC:
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+ switch ((ecx >> 12) & 0xf)
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+ {
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+ case 0:
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+ case 1:
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+ case 2:
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+ case 4:
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+ return (ecx >> 12) & 0xf;
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+ case 6:
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+ return 8;
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+ case 8:
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+ return 16;
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+ case 10:
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+ return 32;
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+ case 11:
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+ return 48;
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+ case 12:
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+ return 64;
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+ case 13:
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+ return 96;
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+ case 14:
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+ return 128;
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+ case 15:
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+ return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);
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+ default:
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+ return 0;
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+ }
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+
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+ case _SC_LEVEL2_CACHE_LINESIZE:
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+ return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
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+
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+ case _SC_LEVEL3_CACHE_SIZE:
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+ {
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+ long int total_l3_cache = 0, l3_cache_per_thread = 0;
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+ unsigned int threads = 0;
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+ const struct cpu_features *cpu_features;
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+
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+ if ((edx & 0xf000) == 0)
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+ return 0;
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+
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+ total_l3_cache = (edx & 0x3ffc0000) << 1;
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+ cpu_features = __get_cpu_features ();
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+
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+ /* Figure out the number of logical threads that share L3. */
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+ if (max_cpuid >= 0x80000008)
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+ {
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+ /* Get width of APIC ID. */
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+ __cpuid (0x80000008, eax, ebx, ecx, edx);
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+ threads = (ecx & 0xff) + 1;
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+ }
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+
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+ if (threads == 0)
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+ {
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+ /* If APIC ID width is not available, use logical
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+ processor count. */
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+ __cpuid (0x00000001, eax, ebx, ecx, edx);
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+ if ((edx & (1 << 28)) != 0)
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+ threads = (ebx >> 16) & 0xff;
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+ }
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+
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+ /* Cap usage of highest cache level to the number of
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+ supported threads. */
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+ if (threads > 0)
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+ l3_cache_per_thread = total_l3_cache/threads;
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+
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+ /* Get shared cache per ccx for Zen architectures. */
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+ if (cpu_features->basic.family >= 0x17)
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+ {
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+ long int l3_cache_per_ccx = 0;
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+ /* Get number of threads share the L3 cache in CCX. */
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+ __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);
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+ unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;
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+ l3_cache_per_ccx = l3_cache_per_thread * threads_per_ccx;
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+ return l3_cache_per_ccx;
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+ }
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+ else
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+ {
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+ return l3_cache_per_thread;
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+ }
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+ }
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+
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case _SC_LEVEL3_CACHE_ASSOC:
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- return ecx ? ((ebx >> 22) & 0x3ff) + 1 : 0;
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- case _SC_LEVEL1_ICACHE_LINESIZE:
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- case _SC_LEVEL1_DCACHE_LINESIZE:
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- case _SC_LEVEL2_CACHE_LINESIZE:
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+ switch ((edx >> 12) & 0xf)
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+ {
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+ case 0:
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+ case 1:
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+ case 2:
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+ case 4:
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+ return (edx >> 12) & 0xf;
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+ case 6:
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+ return 8;
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+ case 8:
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+ return 16;
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+ case 10:
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+ return 32;
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+ case 11:
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+ return 48;
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+ case 12:
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+ return 64;
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+ case 13:
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+ return 96;
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+ case 14:
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+ return 128;
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+ case 15:
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+ return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);
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+ default:
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+ return 0;
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+ }
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+
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case _SC_LEVEL3_CACHE_LINESIZE:
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- return ecx ? (ebx & 0xfff) + 1 : 0;
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- case _SC_LEVEL1_ICACHE_SIZE:
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- case _SC_LEVEL1_DCACHE_SIZE:
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- case _SC_LEVEL2_CACHE_SIZE:
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- case _SC_LEVEL3_CACHE_SIZE:
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- return ecx ? (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1): 0;
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+ return (edx & 0xf000) == 0 ? 0 : edx & 0xff;
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+
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default:
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__builtin_unreachable ();
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}
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@@ -703,7 +869,6 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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data = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
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core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
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- shared_per_thread = shared;
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level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE);
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level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE);
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@@ -716,13 +881,20 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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level3_cache_size = shared;
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level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC);
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level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE);
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+ level4_cache_size = handle_amd (_SC_LEVEL4_CACHE_SIZE);
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if (shared <= 0)
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- /* No shared L3 cache. All we have is the L2 cache. */
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|
- shared = core;
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+ {
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|
+ /* No shared L3 cache. All we have is the L2 cache. */
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|
+ shared = core;
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|
+ }
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+ else if (cpu_features->basic.family < 0x17)
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+ {
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|
+ /* Account for exclusive L2 and L3 caches. */
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+ shared += core;
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|
+ }
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- if (shared_per_thread <= 0)
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- shared_per_thread = shared;
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+ shared_per_thread = shared;
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|
}
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cpu_features->level1_icache_size = level1_icache_size;
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|
--
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|
2.41.0
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|
|
||||||
45
cache-intel-shared.patch
Normal file
45
cache-intel-shared.patch
Normal file
@ -0,0 +1,45 @@
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|
From 5ea70cc02626d9b85f1570153873d8648a47bf95 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Noah Goldstein <goldstein.w.n@gmail.com>
|
||||||
|
Date: Thu, 10 Aug 2023 19:28:24 -0500
|
||||||
|
Subject: [PATCH] x86: Fix incorrect scope of setting `shared_per_thread` [BZ#
|
||||||
|
30745]
|
||||||
|
|
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|
The:
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|
|
||||||
|
```
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|
if (shared_per_thread > 0 && threads > 0)
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|
shared_per_thread /= threads;
|
||||||
|
```
|
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|
|
||||||
|
Code was accidentally moved to inside the else scope. This doesn't
|
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|
match how it was previously (before af992e7abd).
|
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|
|
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|
This patch fixes that by putting the division after the `else` block.
|
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|
|
||||||
|
(cherry picked from commit 084fb31bc2c5f95ae0b9e6df4d3cf0ff43471ede)
|
||||||
|
---
|
||||||
|
sysdeps/x86/dl-cacheinfo.h | 7 +++----
|
||||||
|
1 file changed, 3 insertions(+), 4 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
|
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|
index 285773039f..5ddb35c9d9 100644
|
||||||
|
--- a/sysdeps/x86/dl-cacheinfo.h
|
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|
+++ b/sysdeps/x86/dl-cacheinfo.h
|
||||||
|
@@ -770,11 +770,10 @@ get_common_cache_info (long int *shared_ptr, long int * shared_per_thread_ptr, u
|
||||||
|
level. */
|
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|
threads = ((cpu_features->features[CPUID_INDEX_1].cpuid.ebx >> 16)
|
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|
& 0xff);
|
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|
-
|
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|
- /* Get per-thread size of highest level cache. */
|
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|
- if (shared_per_thread > 0 && threads > 0)
|
||||||
|
- shared_per_thread /= threads;
|
||||||
|
}
|
||||||
|
+ /* Get per-thread size of highest level cache. */
|
||||||
|
+ if (shared_per_thread > 0 && threads > 0)
|
||||||
|
+ shared_per_thread /= threads;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Account for non-inclusive L2 and L3 caches. */
|
||||||
|
--
|
||||||
|
2.41.0
|
||||||
|
|
||||||
@ -1,3 +1,24 @@
|
|||||||
|
Index: glibc-2.38/debug/strcpy_chk.c
|
||||||
|
===================================================================
|
||||||
|
--- glibc-2.38.orig/debug/strcpy_chk.c
|
||||||
|
+++ glibc-2.38/debug/strcpy_chk.c
|
||||||
|
@@ -31,3 +31,4 @@ __strcpy_chk (char *dest, const char *sr
|
||||||
|
|
||||||
|
return memcpy (dest, src, len + 1);
|
||||||
|
}
|
||||||
|
+libc_hidden_builtin_def (__strcpy_chk)
|
||||||
|
Index: glibc-2.38/include/string.h
|
||||||
|
===================================================================
|
||||||
|
--- glibc-2.38.orig/include/string.h
|
||||||
|
+++ glibc-2.38/include/string.h
|
||||||
|
@@ -213,6 +213,7 @@ libc_hidden_builtin_proto (__memcpy_chk)
|
||||||
|
libc_hidden_builtin_proto (__memmove_chk)
|
||||||
|
libc_hidden_builtin_proto (__mempcpy_chk)
|
||||||
|
libc_hidden_builtin_proto (__memset_chk)
|
||||||
|
+libc_hidden_builtin_proto (__strcpy_chk)
|
||||||
|
libc_hidden_builtin_proto (__stpcpy_chk)
|
||||||
|
|
||||||
|
#endif
|
||||||
Index: glibc-2.38/intl/loadmsgcat.c
|
Index: glibc-2.38/intl/loadmsgcat.c
|
||||||
===================================================================
|
===================================================================
|
||||||
--- glibc-2.38.orig/intl/loadmsgcat.c
|
--- glibc-2.38.orig/intl/loadmsgcat.c
|
||||||
|
|||||||
@ -1,3 +1,13 @@
|
|||||||
|
-------------------------------------------------------------------
|
||||||
|
Mon Aug 14 08:12:28 UTC 2023 - Andreas Schwab <schwab@suse.de>
|
||||||
|
|
||||||
|
- Require that elf/check-localplt does not fail
|
||||||
|
- glibc-2.3.90-langpackdir.diff: add hidden alias for __strcpy_chk
|
||||||
|
- cache-amd-legacy.patch: x86: Fix for cache computation on AMD legacy
|
||||||
|
cpus
|
||||||
|
- cache-intel-shared.patch: x86: Fix incorrect scope of setting
|
||||||
|
`shared_per_thread` (BZ# 30745)
|
||||||
|
|
||||||
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
||||||
Wed Aug 2 10:50:32 UTC 2023 - Andreas Schwab <schwab@suse.de>
|
Wed Aug 2 10:50:32 UTC 2023 - Andreas Schwab <schwab@suse.de>
|
||||||
|
|
||||||
|
|||||||
@ -291,6 +291,10 @@ Patch306: glibc-fix-double-loopback.diff
|
|||||||
###
|
###
|
||||||
# PATCH-FIX-OPENSUSE iconv: restore verbosity with unrecognized encoding names (BZ #30694)
|
# PATCH-FIX-OPENSUSE iconv: restore verbosity with unrecognized encoding names (BZ #30694)
|
||||||
Patch1000: iconv-error-verbosity.patch
|
Patch1000: iconv-error-verbosity.patch
|
||||||
|
# PATCH-FIX-OPENSUSE x86: Fix for cache computation on AMD legacy cpus
|
||||||
|
Patch1001: cache-amd-legacy.patch
|
||||||
|
# PATCH-FIX-OPENSUSE x86: Fix incorrect scope of setting `shared_per_thread` (BZ# 30745)
|
||||||
|
Patch1002: cache-intel-shared.patch
|
||||||
|
|
||||||
###
|
###
|
||||||
# Patches awaiting upstream approval
|
# Patches awaiting upstream approval
|
||||||
@ -515,6 +519,8 @@ library in a cross compilation setting.
|
|||||||
|
|
||||||
%if %{without snapshot}
|
%if %{without snapshot}
|
||||||
%patch1000 -p1
|
%patch1000 -p1
|
||||||
|
%patch1001 -p1
|
||||||
|
%patch1002 -p1
|
||||||
%endif
|
%endif
|
||||||
|
|
||||||
%patch2000 -p1
|
%patch2000 -p1
|
||||||
@ -754,6 +760,7 @@ make %{?_smp_mflags} %{?make_output_sync} -C cc-base -k check || {
|
|||||||
# Exceptions:
|
# Exceptions:
|
||||||
# None!
|
# None!
|
||||||
make %{?_smp_mflags} %{?make_output_sync} -C cc-base check-abi
|
make %{?_smp_mflags} %{?make_output_sync} -C cc-base check-abi
|
||||||
|
make %{?_smp_mflags} %{?make_output_sync} -C cc-base test t=elf/check-localplt
|
||||||
%endif
|
%endif
|
||||||
|
|
||||||
%define rtldlib %{_lib}
|
%define rtldlib %{_lib}
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user