diff --git a/llvm-scev-fix-isImpliedViaMerge.patch b/llvm-scev-fix-isImpliedViaMerge.patch
index 7bad43b..629509f 100644
--- a/llvm-scev-fix-isImpliedViaMerge.patch
+++ b/llvm-scev-fix-isImpliedViaMerge.patch
@@ -19,14 +19,14 @@ index 0000000000000..82e1d2252e760
 +
 +declare void @use(i1)
 +
-+define void @test(ptr %arr) {
++define void @test(i32* %arr) {
 +; CHECK-LABEL: @test(
 +; CHECK-NEXT:  entry:
 +; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
 +; CHECK:       loop.header:
 +; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[IV_INC:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
-+; CHECK-NEXT:    [[PTR:%.*]] = getelementptr inbounds i32, ptr [[ARR:%.*]], i64 [[IV]]
-+; CHECK-NEXT:    [[V:%.*]] = load i32, ptr [[PTR]], align 4
++; CHECK-NEXT:    [[PTR:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[IV]]
++; CHECK-NEXT:    [[V:%.*]] = load i32, i32* [[PTR]], align 4
 +; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[V]], 0
 +; CHECK-NEXT:    br i1 [[CMP1]], label [[IF:%.*]], label [[LOOP_LATCH]]
 +; CHECK:       if:
@@ -45,8 +45,8 @@ index 0000000000000..82e1d2252e760
 +loop.header:
 +  %iv = phi i64 [ %iv.inc, %loop.latch ], [ 0, %entry ]
 +  %prev = phi i32 [ %v, %loop.latch ], [ 0, %entry ]
-+  %ptr = getelementptr inbounds i32, ptr %arr, i64 %iv
-+  %v = load i32, ptr %ptr
++  %ptr = getelementptr inbounds i32, i32* %arr, i64 %iv
++  %v = load i32, i32* %ptr
 +  %cmp1 = icmp sgt i32 %v, 0
 +  br i1 %cmp1, label %if, label %loop.latch
 +
@@ -136,14 +136,14 @@ diff --git a/llvm/test/Transforms/IndVarSimplify/pr56242.ll b/llvm/test/Transfor
 index 82e1d2252e760..6afed4177e1f7 100644
 --- a/llvm/test/Transforms/IndVarSimplify/pr56242.ll
 +++ b/llvm/test/Transforms/IndVarSimplify/pr56242.ll
-@@ -9,12 +9,14 @@ define void @test(ptr %arr) {
+@@ -9,12 +9,14 @@ define void @test(i32* %arr) {
  ; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
  ; CHECK:       loop.header:
  ; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[IV_INC:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
 +; CHECK-NEXT:    [[PREV:%.*]] = phi i32 [ [[V:%.*]], [[LOOP_LATCH]] ], [ 0, [[ENTRY]] ]
- ; CHECK-NEXT:    [[PTR:%.*]] = getelementptr inbounds i32, ptr [[ARR:%.*]], i64 [[IV]]
--; CHECK-NEXT:    [[V:%.*]] = load i32, ptr [[PTR]], align 4
-+; CHECK-NEXT:    [[V]] = load i32, ptr [[PTR]], align 4
+ ; CHECK-NEXT:    [[PTR:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[IV]]
+-; CHECK-NEXT:    [[V:%.*]] = load i32, i32* [[PTR]], align 4
++; CHECK-NEXT:    [[V]] = load i32, i32* [[PTR]], align 4
  ; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[V]], 0
  ; CHECK-NEXT:    br i1 [[CMP1]], label [[IF:%.*]], label [[LOOP_LATCH]]
  ; CHECK:       if: