forked from pool/llvm15
3771228637
* This release contains bug-fixes for the LLVM 15.0.0 release.
This release is API and ABI compatible with 15.0.0.
- Add llvm-armv7-fix-vector-compare-with-zero-lowering.patch: Fix
lowering of non-canonical vector comparison with zero on armv7,
preventing a crash (boo#1204267, gh#llvm/llvm-project#58514).
- Add lldb-swig-4.1.0-build-fix.patch: Fix build with Swig 4.1.0.
- Rebase llvm-do-not-install-static-libraries.patch.
OBS-URL: https://build.opensuse.org/package/show/devel:tools:compiler/llvm15?expand=0&rev=7
147 lines
5.4 KiB
Diff
147 lines
5.4 KiB
Diff
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
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===================================================================
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--- llvm/lib/Target/ARM/ARMISelLowering.cpp
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+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
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@@ -6833,25 +6833,25 @@
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// If one of the operands is a constant vector zero, attempt to fold the
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// comparison to a specialized compare-against-zero form.
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- SDValue SingleOp;
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- if (ISD::isBuildVectorAllZeros(Op1.getNode()))
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- SingleOp = Op0;
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- else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
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+ if (ISD::isBuildVectorAllZeros(Op0.getNode()) &&
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+ (Opc == ARMCC::GE || Opc == ARMCC::GT || Opc == ARMCC::EQ ||
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+ Opc == ARMCC::NE)) {
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if (Opc == ARMCC::GE)
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Opc = ARMCC::LE;
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else if (Opc == ARMCC::GT)
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Opc = ARMCC::LT;
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- SingleOp = Op1;
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+ std::swap(Op0, Op1);
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}
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SDValue Result;
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- if (SingleOp.getNode()) {
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- Result = DAG.getNode(ARMISD::VCMPZ, dl, CmpVT, SingleOp,
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+ if (ISD::isBuildVectorAllZeros(Op1.getNode()) &&
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+ (Opc == ARMCC::GE || Opc == ARMCC::GT || Opc == ARMCC::LE ||
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+ Opc == ARMCC::LT || Opc == ARMCC::NE || Opc == ARMCC::EQ))
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+ Result = DAG.getNode(ARMISD::VCMPZ, dl, CmpVT, Op0,
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DAG.getConstant(Opc, dl, MVT::i32));
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- } else {
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+ else
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Result = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1,
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DAG.getConstant(Opc, dl, MVT::i32));
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- }
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Result = DAG.getSExtOrTrunc(Result, dl, VT);
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Index: llvm/test/CodeGen/Thumb2/mve-pred-and.ll
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===================================================================
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--- llvm/test/CodeGen/Thumb2/mve-pred-and.ll
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+++ llvm/test/CodeGen/Thumb2/mve-pred-and.ll
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@@ -122,8 +122,9 @@
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define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpulez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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+; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vpt.i32 eq, q0, zr
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-; CHECK-NEXT: vcmpt.u32 cs, q1, zr
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+; CHECK-NEXT: vcmpt.u32 cs, q2, q1
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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Index: llvm/test/CodeGen/Thumb2/mve-pred-or.ll
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===================================================================
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--- llvm/test/CodeGen/Thumb2/mve-pred-or.ll
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+++ llvm/test/CodeGen/Thumb2/mve-pred-or.ll
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@@ -123,7 +123,8 @@
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define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpulez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u32 cs, q1, zr
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+; CHECK-NEXT: vmov.i32 q2, #0x0
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+; CHECK-NEXT: vcmp.u32 cs, q2, q1
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 ne, q0, zr
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Index: llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
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===================================================================
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--- llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
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+++ llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
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@@ -151,7 +151,8 @@
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define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: cmpulez_v4i1:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u32 cs, q1, zr
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+; CHECK-NEXT: vmov.i32 q2, #0x0
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+; CHECK-NEXT: vcmp.u32 cs, q2, q1
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vmrs r1, p0
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Index: llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
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===================================================================
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--- llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
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+++ llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
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@@ -110,7 +110,8 @@
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define arm_aapcs_vfpcc <4 x i32> @vcmp_ulez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: vcmp_ulez_v4i32:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u32 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u32 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -229,7 +230,8 @@
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define arm_aapcs_vfpcc <8 x i16> @vcmp_ulez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: vcmp_ulez_v8i16:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u16 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u16 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -348,7 +350,8 @@
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define arm_aapcs_vfpcc <16 x i8> @vcmp_ulez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vcmp_ulez_v16i8:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u8 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u8 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -489,7 +492,8 @@
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define arm_aapcs_vfpcc <4 x i32> @vcmp_r_ugez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: vcmp_r_ugez_v4i32:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u32 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u32 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -608,7 +612,8 @@
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define arm_aapcs_vfpcc <8 x i16> @vcmp_r_ugez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: vcmp_r_ugez_v8i16:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u16 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u16 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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@@ -727,7 +732,8 @@
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define arm_aapcs_vfpcc <16 x i8> @vcmp_r_ugez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vcmp_r_ugez_v16i8:
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; CHECK: @ %bb.0: @ %entry
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-; CHECK-NEXT: vcmp.u8 cs, q0, zr
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+; CHECK-NEXT: vmov.i32 q3, #0x0
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+; CHECK-NEXT: vcmp.u8 cs, q3, q0
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; CHECK-NEXT: vpsel q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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