forked from pool/mcelog
c729908bac
- Includes following SLE 15 SP5 jira features: * jsc#PED-671 mcelog: Update to latest release * jsc#PED-686 [CPU Features] Update mcelog support for ADL-N * jsc#PED-638 [CPU Features] Update mcelog support for MTL-P - Update to version 189: - Had to adopt to latest CPU identification model mainline patch: b54ee05056a76e mcelog: Drop CASE_INTEL define and friends A add_new_amd_cpu_defines D add-defines.patch M Start-consolidating-AMD-specific-stuff.patch M add-f10h-support.patch M add-f11h-support.patch M add-f12h-support.patch M add-f14h-support.patch M add-f15h-support.patch M add-f16h-support.patch M email.patch M fix_setgroups_missing_call.patch OBS-URL: https://build.opensuse.org/request/show/1092613 OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=104
96 lines
2.1 KiB
Diff
96 lines
2.1 KiB
Diff
Add F16h decoding support
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Signed-off-by: Borislav Petkov <bp@suse.de>
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---
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amd.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
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amd.h | 3 ++-
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mcelog.c | 2 ++
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mcelog.h | 1 +
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4 files changed, 58 insertions(+), 1 deletion(-)
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Index: mcelog-189/amd.c
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===================================================================
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--- mcelog-189.orig/amd.c
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+++ mcelog-189/amd.c
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@@ -200,6 +200,8 @@ enum cputype select_amd_cputype(u32 fami
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return CPU_F14H;
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case 0x15:
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return CPU_F15H;
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+ case 0x16:
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+ return CPU_F16H;
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default:
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break;
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}
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@@ -687,6 +689,47 @@ static bool f15h_mc2_mce(u16 ec, u8 xec)
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return ret;
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}
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+static bool f16h_mc2_mce(u16 ec, u8 xec)
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+{
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+ u8 r4 = R4(ec);
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+
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+ if (!MEM_ERROR(ec))
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+ return false;
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+
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+ switch (xec) {
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+ case 0x04 ... 0x05:
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+ Wprintf("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
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+ break;
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+
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+ case 0x09 ... 0x0b:
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+ case 0x0d ... 0x0f:
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+ Wprintf("ECC error in L2 tag (%s).\n",
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+ ((r4 == R4_GEN) ? "BankReq" :
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+ ((r4 == R4_SNOOP) ? "Prb" : "Fill")));
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+ break;
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+
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+ case 0x10 ... 0x19:
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+ case 0x1b:
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+ Wprintf("ECC error in L2 data array (%s).\n",
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+ (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" :
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+ ((r4 == R4_GEN) ? "Attr" :
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+ ((r4 == R4_EVICT) ? "Vict" : "Fill"))));
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+ break;
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+
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+ case 0x1c ... 0x1d:
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+ case 0x1f:
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+ Wprintf("Parity error in L2 attribute bits (%s).\n",
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+ ((r4 == R4_RD) ? "Hit" :
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+ ((r4 == R4_GEN) ? "Attr" : "Fill")));
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+ break;
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+
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+ default:
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+ return false;
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+ }
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+
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+ return true;
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+}
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+
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static void decode_mc2_mce(struct amd_decoder_ops *ops, struct mce *m)
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{
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u16 ec = EC(m->status);
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@@ -897,6 +940,12 @@ struct amd_decoder_ops fam_ops[] = {
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.mc1_mce = f15h_mc1_mce,
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.mc2_mce = f15h_mc2_mce,
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},
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+ [AMD_F16H] = {
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+ .cpu = AMD_F16H,
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+ .mc0_mce = cat_mc0_mce,
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+ .mc1_mce = cat_mc1_mce,
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+ .mc2_mce = f16h_mc2_mce,
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+ },
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};
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static void __decode_amd_mc(enum cputype cpu, struct mce *mce)
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@@ -920,6 +969,10 @@ static void __decode_amd_mc(enum cputype
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xec_mask = 0x1f;
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ops = &fam_ops[AMD_F15H];
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break;
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+ case CPU_F16H:
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+ xec_mask = 0x1f;
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+ ops = &fam_ops[AMD_F16H];
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+ break;
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default:
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Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
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return;
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