forked from pool/mcelog
277832baf3
(by trenn@suse.de) - Update to version 1.60 (fate#326221): * Turn back rb_color field into unsigned long * trigger: add a sync argument for waiting trigger child process exit * page: trigger: add pre/post sync trigger when doing soft memory offline * fixed build errors for some lose code when merging code * transfer the page address to pre/post-sync-trigger scripts * mcelog: Fix "--ascii" parsing to cope with change in kernel output since v4.10 * Remove now unused local variable * Add scripts file to do MCA error code validation for a selected CPU model * Add license file * mcelog: Improve decoding for APEI reported errors OBS-URL: https://build.opensuse.org/request/show/637679 OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=71
91 lines
2.6 KiB
Diff
91 lines
2.6 KiB
Diff
Add F12h decoding support
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Signed-off-by: Borislav Petkov <bp@suse.de>
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Index: mcelog-1.60/amd.c
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===================================================================
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--- mcelog-1.60.orig/amd.c 2018-09-24 15:15:10.454960116 +0200
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+++ mcelog-1.60/amd.c 2018-09-24 15:15:15.607266576 +0200
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@@ -157,6 +157,8 @@ enum cputype select_amd_cputype(u32 fami
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return CPU_F10H;
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case 0x11:
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return CPU_F11H;
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+ case 0x12:
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+ return CPU_F12H;
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default:
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break;
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}
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@@ -648,6 +650,12 @@ struct amd_decoder_ops fam_ops[] = {
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.mc1_mce = k8_mc1_mce,
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.mc2_mce = k8_mc2_mce,
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},
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+ [AMD_F12H] = {
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+ .cpu = AMD_F12H,
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+ .mc0_mce = f12h_mc0_mce,
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+ .mc1_mce = k8_mc1_mce,
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+ .mc2_mce = k8_mc2_mce,
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+ },
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};
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static void __decode_amd_mc(enum cputype cpu, struct mce *mce)
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@@ -661,6 +669,9 @@ static void __decode_amd_mc(enum cputype
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case CPU_F11H:
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ops = &fam_ops[AMD_F11H];
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break;
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+ case CPU_F12H:
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+ ops = &fam_ops[AMD_F12H];
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+ break;
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default:
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Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
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return;
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Index: mcelog-1.60/amd.h
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===================================================================
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--- mcelog-1.60.orig/amd.h 2018-09-24 15:15:10.454960116 +0200
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+++ mcelog-1.60/amd.h 2018-09-24 15:15:15.607266576 +0200
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@@ -9,6 +9,7 @@ enum amdcpu {
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AMD_K8 = 0,
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AMD_F10H,
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AMD_F11H,
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+ AMD_F12H,
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AMD_F14H,
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AMD_F15H,
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AMD_F16H,
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@@ -94,4 +95,5 @@ enum rrrr_ids {
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#define CASE_AMD_CPUS \
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case CPU_K8: \
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case CPU_F10H: \
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- case CPU_F11H
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+ case CPU_F11H: \
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+ case CPU_F12H
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Index: mcelog-1.60/mcelog.h
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===================================================================
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--- mcelog-1.60.orig/mcelog.h 2018-09-24 15:15:10.454960116 +0200
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+++ mcelog-1.60/mcelog.h 2018-09-24 15:15:15.607266576 +0200
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@@ -119,6 +119,7 @@ enum cputype {
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CPU_K8,
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CPU_F10H,
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CPU_F11H,
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+ CPU_F12H,
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CPU_P4,
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CPU_NEHALEM,
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CPU_DUNNINGTON,
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Index: mcelog-1.60/mcelog.c
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===================================================================
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--- mcelog-1.60.orig/mcelog.c 2018-09-24 15:15:10.458960355 +0200
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+++ mcelog-1.60/mcelog.c 2018-09-24 15:15:15.611266814 +0200
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@@ -229,6 +229,7 @@ static char *cputype_name[] = {
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[CPU_K8] = "AMD K8 and derivates",
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[CPU_F10H] = "AMD Greyhound",
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[CPU_F11H] = "AMD Griffin",
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+ [CPU_F12H] = "AMD Llano",
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[CPU_P4] = "Intel P4",
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[CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")",
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[CPU_DUNNINGTON] = "Intel Xeon 7400 series",
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@@ -260,6 +261,7 @@ static struct config_choice cpu_choices[
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{ "k8", CPU_K8 },
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{ "f10h", CPU_F10H },
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{ "f11h", CPU_F11H },
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+ { "f12h", CPU_F12H },
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{ "p4", CPU_P4 },
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{ "dunnington", CPU_DUNNINGTON },
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{ "xeon74xx", CPU_DUNNINGTON },
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