forked from pool/mcelog
1c1607eb66
- Add mce decoding support for latest AMD CPUs (bnc#871881). - Implementation done by Borislav Petkov <bp@suse.de> * Add patches/Start-consolidating-AMD-specific-stuff.patch * Add add-defines.patch * Add add-f10h-support.patch * Add add-f11h-support.patch * Add add-f12h-support.patch * Add add-f14h-support.patch * Add add-f15h-support.patch * Add add-f16h-support.patch OBS-URL: https://build.opensuse.org/request/show/234343 OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=35
74 lines
1.7 KiB
Diff
74 lines
1.7 KiB
Diff
Add AMD-specific defines and helpers
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Signed-off-by: Borislav Petkov <bp@suse.de>
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Index: mcelog/amd.h
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===================================================================
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--- mcelog.orig/amd.h 2014-05-08 01:10:26.000000000 +0200
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+++ mcelog/amd.h 2014-05-08 01:18:50.000000000 +0200
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@@ -10,5 +10,65 @@ int mce_filter_k8(struct mce *m);
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#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2)
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#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3)
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+#define EC(x) ((x) & 0xffff)
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+#define XEC(x, mask) (((x) >> 16) & mask)
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+
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+#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
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+#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
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+
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+#define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010)
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+#define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100)
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+#define BUS_ERROR(x) (((x) & 0xF800) == 0x0800)
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+#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400)
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+
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+#define TT(x) (((x) >> 2) & 0x3)
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+#define TT_MSG(x) tt_msgs[TT(x)]
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+#define II(x) (((x) >> 2) & 0x3)
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+#define II_MSG(x) ii_msgs[II(x)]
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+#define LL(x) ((x) & 0x3)
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+#define LL_MSG(x) ll_msgs[LL(x)]
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+#define TO(x) (((x) >> 8) & 0x1)
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+#define TO_MSG(x) to_msgs[TO(x)]
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+#define PP(x) (((x) >> 9) & 0x3)
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+#define PP_MSG(x) pp_msgs[PP(x)]
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+#define UU(x) (((x) >> 8) & 0x3)
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+#define UU_MSG(x) uu_msgs[UU(x)]
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+
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+#define R4(x) (((x) >> 4) & 0xf)
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+#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
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+
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#define CASE_AMD_CPUS \
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case CPU_K8
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+
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+enum tt_ids {
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+ TT_INSTR = 0,
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+ TT_DATA,
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+ TT_GEN,
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+ TT_RESV,
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+};
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+
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+enum ll_ids {
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+ LL_RESV = 0,
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+ LL_L1,
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+ LL_L2,
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+ LL_LG,
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+};
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+
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+enum ii_ids {
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+ II_MEM = 0,
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+ II_RESV,
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+ II_IO,
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+ II_GEN,
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+};
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+
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+enum rrrr_ids {
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+ R4_GEN = 0,
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+ R4_RD,
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+ R4_WR,
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+ R4_DRD,
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+ R4_DWR,
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+ R4_IRD,
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+ R4_PREF,
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+ R4_EVICT,
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+ R4_SNOOP,
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+};
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