From e8d12670642e37997c024152e5b9a89af65445c3052530a6f146ba2f95c9d07a Mon Sep 17 00:00:00 2001 From: Peter Simons Date: Fri, 30 Oct 2020 13:39:09 +0000 Subject: [PATCH] Accepting request 844781 from home:pgajdos - Add decode support for RCECs [jsc#SLE-13735] - added patches https://github.com/pciutils/pciutils/commit/e12bd01eea67ca8cf539263124843ba281eb6ecc + pciutils-add-decode-support-for-RCECs.patch OBS-URL: https://build.opensuse.org/request/show/844781 OBS-URL: https://build.opensuse.org/package/show/Base:System/pciutils?expand=0&rev=74 --- pciutils-add-decode-support-for-RCECs.patch | 422 ++++++++++++++++++++ pciutils.changes | 8 + pciutils.spec | 2 + 3 files changed, 432 insertions(+) create mode 100644 pciutils-add-decode-support-for-RCECs.patch diff --git a/pciutils-add-decode-support-for-RCECs.patch b/pciutils-add-decode-support-for-RCECs.patch new file mode 100644 index 0000000..09ca746 --- /dev/null +++ b/pciutils-add-decode-support-for-RCECs.patch @@ -0,0 +1,422 @@ +diff --git a/lib/header.h b/lib/header.h +index 472816e..57a9343 100644 +--- a/lib/header.h ++++ b/lib/header.h +@@ -219,7 +219,7 @@ + #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ + #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */ + #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */ +-#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ ++#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ + #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ + #define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */ + #define PCI_EXT_CAP_ID_RCRB 0x0a /* Root Complex Register Block */ +@@ -1048,6 +1048,12 @@ + #define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */ + #define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */ + ++/* Root Complex Event Collector Endpoint Association */ ++#define PCI_RCEC_EP_CAP_VER(reg) (((reg) >> 16) & 0xf) ++#define PCI_RCEC_BUSN_REG_VER 0x02 /* as per PCIe sec 7.9.10.1 */ ++#define PCI_RCEC_RCIEP_BMAP 0x0004 /* as per PCIe sec 7.9.10.2 */ ++#define PCI_RCEC_BUSN_REG 0x0008 /* as per PCIe sec 7.9.10.3 */ ++ + /* PCIe Vendor-Specific Capability */ + #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */ + #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */ +diff --git a/ls-ecaps.c b/ls-ecaps.c +index e71209e..99c55ff 100644 +--- a/ls-ecaps.c ++++ b/ls-ecaps.c +@@ -634,6 +634,61 @@ cap_rclink(struct device *d, int where) + } + } + ++static void ++cap_rcec(struct device *d, int where) ++{ ++ printf("Root Complex Event Collector Endpoint Association\n"); ++ if (verbose < 2) ++ return; ++ ++ if (!config_fetch(d, where, 12)) ++ return; ++ ++ u32 hdr = get_conf_long(d, where); ++ byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr); ++ u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP); ++ printf("\t\tRCiEPBitmap: "); ++ if (bmap) ++ { ++ int prevmatched=0; ++ int adjcount=0; ++ int prevdev=0; ++ printf("RCiEP at Device(s):"); ++ for (int dev=0; dev < 32; dev++) ++ { ++ if (BITS(bmap, dev, 1)) ++ { ++ if (!adjcount) ++ printf("%s %u", (prevmatched) ? "," : "", dev); ++ adjcount++; ++ prevdev=dev; ++ prevmatched=1; ++ } ++ else ++ { ++ if (adjcount > 1) ++ printf("-%u", prevdev); ++ adjcount=0; ++ } ++ } ++ } ++ else ++ printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]"); ++ printf("\n"); ++ ++ if (cap_ver < PCI_RCEC_BUSN_REG_VER) ++ return; ++ ++ u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG); ++ u8 lastbusn = BITS(busn, 16, 8); ++ u8 nextbusn = BITS(busn, 8, 8); ++ ++ if ((lastbusn == 0x00) && (nextbusn == 0xff)) ++ printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]"); ++ else ++ printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn ); ++} ++ + static void + cap_dvsec_cxl(struct device *d, int where) + { +@@ -991,8 +1046,8 @@ show_ext_caps(struct device *d, int type) + case PCI_EXT_CAP_ID_RCILINK: + printf("Root Complex Internal Link \n"); + break; +- case PCI_EXT_CAP_ID_RCECOLL: +- printf("Root Complex Event Collector \n"); ++ case PCI_EXT_CAP_ID_RCEC: ++ cap_rcec(d, where); + break; + case PCI_EXT_CAP_ID_MFVC: + printf("Multi-Function Virtual Channel \n"); +diff --git a/setpci.c b/setpci.c +index 90ca726..2cb70fa 100644 +--- a/setpci.c ++++ b/setpci.c +@@ -350,7 +350,7 @@ static const struct reg_name pci_reg_names[] = { + { 0x20004, 0, 0, "ECAP_PB" }, + { 0x20005, 0, 0, "ECAP_RCLINK" }, + { 0x20006, 0, 0, "ECAP_RCILINK" }, +- { 0x20007, 0, 0, "ECAP_RCECOLL" }, ++ { 0x20007, 0, 0, "ECAP_RCEC" }, + { 0x20008, 0, 0, "ECAP_MFVC" }, + { 0x20009, 0, 0, "ECAP_VC2" }, + { 0x2000a, 0, 0, "ECAP_RBCB" }, +diff --git a/tests/cap-rcec b/tests/cap-rcec +new file mode 100644 +index 0000000..836d9a1 +--- /dev/null ++++ b/tests/cap-rcec +@@ -0,0 +1,299 @@ ++6a:00.4 Generic system peripheral [0807]: Intel Corporation Device 0b23 ++ Subsystem: Intel Corporation Device 0000 ++ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- ++ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- diff --git a/pciutils.spec b/pciutils.spec index 1ca4d32..cdaf985 100644 --- a/pciutils.spec +++ b/pciutils.spec @@ -32,6 +32,8 @@ Source3: https://mj.ucw.cz/pgpkey.txt#/%{name}.keyring Patch1: pciutils-3.1.9_pkgconfig.patch Patch2: pciutils-ocloexec.patch Patch3: pciutils-endianh.patch +# https://github.com/pciutils/pciutils/commit/e12bd01eea67ca8cf539263124843ba281eb6ecc +Patch4: pciutils-add-decode-support-for-RCECs.patch BuildRequires: pkgconfig BuildRequires: pkgconfig(libkmod) BuildRequires: pkgconfig(zlib)