46 lines
1.7 KiB
Diff
46 lines
1.7 KiB
Diff
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Tue, 12 Jan 2021 20:26:47 -1000
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Subject: target/arm: Introduce PREDDESC field definitions
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Git-commit: b64ee454a4a086ed459bcda4c0bbb54e197841e4
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SVE predicate operations cannot use the "usual" simd_desc
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encoding, because the lengths are not a multiple of 8.
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But we were abusing the SIMD_* fields to store values anyway.
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This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214.
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Introduce a new set of field definitions for exclusive use
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of predicates, so that it is obvious what kind of predicate
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we are manipulating. To be used in future patches.
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20210113062650.593824-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/arm/internals.h | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/target/arm/internals.h b/target/arm/internals.h
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index 5460678756d3c4e5f34abe5f6411..73698587d6b8eeffd6ccd1515e7a 100644
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--- a/target/arm/internals.h
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+++ b/target/arm/internals.h
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@@ -1312,6 +1312,15 @@ void arm_log_exception(int idx);
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#define LOG2_TAG_GRANULE 4
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#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
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+/*
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+ * SVE predicates are 1/8 the size of SVE vectors, and cannot use
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+ * the same simd_desc() encoding due to restrictions on size.
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+ * Use these instead.
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+ */
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+FIELD(PREDDESC, OPRSZ, 0, 6)
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+FIELD(PREDDESC, ESZ, 6, 2)
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+FIELD(PREDDESC, DATA, 8, 24)
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+
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/*
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* The SVE simd_data field, for memory ops, contains either
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* rd (5 bits) or a shift count (2 bits).
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