64 lines
2.3 KiB
Diff
64 lines
2.3 KiB
Diff
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From 5c37a7c504f63919341d277486e941c64584d171 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Thu, 10 May 2018 18:10:58 +0100
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Subject: [PATCH] target/arm: Clear SVE high bits for FMOV
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Use write_fp_dreg and clear_vec_high to zero the bits
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that need zeroing for these cases.
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Cc: qemu-stable@nongnu.org
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20180502221552.3873-5-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 9a9f1f59521f46e8ff4527d9a2b52f83577e2aa3)
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/arm/translate-a64.c | 17 +++++------------
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1 file changed, 5 insertions(+), 12 deletions(-)
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diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
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index c91329249d..a2c26a5f0a 100644
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--- a/target/arm/translate-a64.c
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+++ b/target/arm/translate-a64.c
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@@ -5438,31 +5438,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
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if (itof) {
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TCGv_i64 tcg_rn = cpu_reg(s, rn);
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+ TCGv_i64 tmp;
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switch (type) {
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case 0:
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- {
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/* 32 bit */
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- TCGv_i64 tmp = tcg_temp_new_i64();
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+ tmp = tcg_temp_new_i64();
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tcg_gen_ext32u_i64(tmp, tcg_rn);
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- tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));
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- tcg_gen_movi_i64(tmp, 0);
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- tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
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+ write_fp_dreg(s, rd, tmp);
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tcg_temp_free_i64(tmp);
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break;
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- }
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case 1:
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- {
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/* 64 bit */
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- TCGv_i64 tmp = tcg_const_i64(0);
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- tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));
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- tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
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- tcg_temp_free_i64(tmp);
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+ write_fp_dreg(s, rd, tcg_rn);
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break;
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- }
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case 2:
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/* 64 bit to top half. */
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tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
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+ clear_vec_high(s, true, rd);
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break;
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}
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} else {
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