102 lines
4.8 KiB
Diff
102 lines
4.8 KiB
Diff
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From 0fb8a7de8e8013362922d802db7eda5f9bf37766 Mon Sep 17 00:00:00 2001
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From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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Date: Wed, 16 Apr 2014 20:20:52 -0700
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Subject: [PATCH] arm: translate.c: Fix smlald Instruction
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The smlald (and probably smlsld) instruction was doing incorrect sign
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extensions of the operands amongst 64bit result calculation. The
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instruction psuedo-code is:
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operand2 = if m_swap then ROR(R[m],16) else R[m];
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product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
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product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
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result = product1 + product2 + SInt(R[dHi]:R[dLo]);
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R[dHi] = result<63:32>;
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R[dLo] = result<31:0>;
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The result calculation should be done in 64 bit arithmetic, and hence
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product1 and product2 should be sign extended to 64b before calculation.
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The current implementation was adding product1 and product2 together
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then sign-extending the intermediate result leading to false negatives.
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E.G. if product1 = product2 = 0x4000000, their sum = 0x80000000, which
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will be incorrectly interpreted as -ve on sign extension.
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We fix by doing the 64b extensions on both product1 and product2 before
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any addition/subtraction happens.
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We also fix where we were possibly incorrectly setting the Q saturation
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flag for SMLSLD, which the ARM ARM specifically says is not set.
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Reported-by: Christina Smith <christina.smith@xilinx.com>
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Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 2cddb6f5a15be4ab8d2160f3499d128ae93d304d.1397704570.git.peter.crosthwaite@xilinx.com
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 33bbd75a7c3321432fe40a8cbacd64619c56138c)
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Signed-off-by: Andreas Färber <afaerber@suse.de>
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---
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target-arm/translate.c | 34 +++++++++++++++++++++++-----------
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1 file changed, 23 insertions(+), 11 deletions(-)
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diff --git a/target-arm/translate.c b/target-arm/translate.c
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index 56e3b4b..0335f10 100644
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--- a/target-arm/translate.c
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+++ b/target-arm/translate.c
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@@ -8328,27 +8328,39 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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if (insn & (1 << 5))
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gen_swap_half(tmp2);
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gen_smul_dual(tmp, tmp2);
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- if (insn & (1 << 6)) {
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- /* This subtraction cannot overflow. */
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- tcg_gen_sub_i32(tmp, tmp, tmp2);
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- } else {
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- /* This addition cannot overflow 32 bits;
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- * however it may overflow considered as a signed
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- * operation, in which case we must set the Q flag.
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- */
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- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
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- }
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- tcg_temp_free_i32(tmp2);
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if (insn & (1 << 22)) {
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/* smlald, smlsld */
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+ TCGv_i64 tmp64_2;
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+
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tmp64 = tcg_temp_new_i64();
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+ tmp64_2 = tcg_temp_new_i64();
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tcg_gen_ext_i32_i64(tmp64, tmp);
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+ tcg_gen_ext_i32_i64(tmp64_2, tmp2);
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tcg_temp_free_i32(tmp);
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+ tcg_temp_free_i32(tmp2);
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+ if (insn & (1 << 6)) {
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+ tcg_gen_sub_i64(tmp64, tmp64, tmp64_2);
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+ } else {
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+ tcg_gen_add_i64(tmp64, tmp64, tmp64_2);
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+ }
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+ tcg_temp_free_i64(tmp64_2);
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gen_addq(s, tmp64, rd, rn);
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gen_storeq_reg(s, rd, rn, tmp64);
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tcg_temp_free_i64(tmp64);
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} else {
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/* smuad, smusd, smlad, smlsd */
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+ if (insn & (1 << 6)) {
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+ /* This subtraction cannot overflow. */
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+ tcg_gen_sub_i32(tmp, tmp, tmp2);
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+ } else {
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+ /* This addition cannot overflow 32 bits;
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+ * however it may overflow considered as a
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+ * signed operation, in which case we must set
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+ * the Q flag.
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+ */
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+ gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
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+ }
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+ tcg_temp_free_i32(tmp2);
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if (rd != 15)
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{
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tmp2 = load_reg(s, rd);
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