46 lines
1.7 KiB
Diff
46 lines
1.7 KiB
Diff
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Fri, 20 Sep 2019 18:40:39 +0100
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Subject: hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
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Git-commit: ece628fcf69cbbd4b3efb6fbd203af07609467a2
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If we're booting a Linux kernel directly into Non-Secure
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state on a CPU which has Secure state, then make sure we
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set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed
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to access the FPU. Otherwise an AArch32 kernel will UNDEF as
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soon as it tries to use the FPU.
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It used to not matter that we didn't do this until commit
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fc1120a7f5f2d4b6, where we implemented actually honouring
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these NSACR bits.
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The problem only exists for CPUs where EL3 is AArch32; the
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equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to
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not trap, 1 to trap", so the reset value of the register
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permits NS access, unlike NSACR.
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Fixes: fc1120a7f5
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Fixes: https://bugs.launchpad.net/qemu/+bug/1844597
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20190920174039.3916-1-peter.maydell@linaro.org
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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hw/arm/boot.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/hw/arm/boot.c b/hw/arm/boot.c
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index c2b89b3bb9b6b92b0293d859712e..fc4e021a38a6bc1e5e2aa5b5876c 100644
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--- a/hw/arm/boot.c
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+++ b/hw/arm/boot.c
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@@ -754,6 +754,8 @@ static void do_cpu_reset(void *opaque)
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(cs != first_cpu || !info->secure_board_setup)) {
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/* Linux expects non-secure state */
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env->cp15.scr_el3 |= SCR_NS;
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+ /* Set NSACR.{CP11,CP10} so NS can access the FPU */
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+ env->cp15.nsacr |= 3 << 10;
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}
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}
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