84 lines
3.5 KiB
Diff
84 lines
3.5 KiB
Diff
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From df632501e0417ab9814f2a69d7e2859c22b74010 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <rth@twiddle.net>
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Date: Tue, 1 Sep 2015 15:58:02 -0400
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Subject: [PATCH] tcg/aarch64: Fix tcg_out_qemu_{ld, st} for guest_base == 0
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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In ffc6372851d8631a9f9fa56ec613b3244dc635b9, we swapped the guest
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base to the address base register from the address index register.
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Except that 31 in the base slot is SP not XZR, so we need to be
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more intelligent about which reg gets placed in which slot.
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Cc: qemu-stable@nongnu.org (v2.4.0)
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Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
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Reported-by: Andreas Färber <afaerber@suse.de>
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Signed-off-by: Richard Henderson <rth@twiddle.net>
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(cherry picked from commit 352bcb0a2b816ff9ab9d75d0f2384650d9e9ab19)
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[AF: Backported to GUEST_BASE and CONFIG_USE_GUEST_BASE]
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Signed-off-by: Andreas Färber <afaerber@suse.de>
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---
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tcg/aarch64/tcg-target.c | 27 ++++++++++++++++++++-------
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1 file changed, 20 insertions(+), 7 deletions(-)
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diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
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index b7ec4f5..354c89d 100644
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--- a/tcg/aarch64/tcg-target.c
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+++ b/tcg/aarch64/tcg-target.c
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@@ -56,6 +56,11 @@ static const int tcg_target_call_oarg_regs[1] = {
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#define TCG_REG_TMP TCG_REG_X30
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#ifndef CONFIG_SOFTMMU
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+/* Note that XZR cannot be encoded in the address base register slot,
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+ as that actaully encodes SP. So if we need to zero-extend the guest
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+ address, via the address index register slot, we need to load even
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+ a zero guest base into a register. */
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+# define USE_GUEST_BASE (GUEST_BASE != 0 || TARGET_LONG_BITS == 32)
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# ifdef CONFIG_USE_GUEST_BASE
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# define TCG_REG_GUEST_BASE TCG_REG_X28
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# else
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@@ -1216,9 +1221,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
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s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
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- GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR,
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- otype, addr_reg);
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+ if (USE_GUEST_BASE) {
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+ tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
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+ TCG_REG_GUEST_BASE, otype, addr_reg);
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+ } else {
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+ tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
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+ addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
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+ }
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#endif /* CONFIG_SOFTMMU */
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}
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@@ -1238,9 +1247,13 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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add_qemu_ldst_label(s, false, oi, s_bits == MO_64, data_reg, addr_reg,
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s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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- tcg_out_qemu_st_direct(s, memop, data_reg,
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- GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR,
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- otype, addr_reg);
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+ if (USE_GUEST_BASE) {
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+ tcg_out_qemu_st_direct(s, memop, data_reg,
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+ TCG_REG_GUEST_BASE, otype, addr_reg);
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+ } else {
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+ tcg_out_qemu_st_direct(s, memop, data_reg,
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+ addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
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+ }
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#endif /* CONFIG_SOFTMMU */
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}
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@@ -1795,7 +1808,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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CPU_TEMP_BUF_NLONGS * sizeof(long));
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#if defined(CONFIG_USE_GUEST_BASE)
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- if (GUEST_BASE) {
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+ if (USE_GUEST_BASE) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, GUEST_BASE);
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE);
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}
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