42 lines
1.8 KiB
Diff
42 lines
1.8 KiB
Diff
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Thu, 22 Aug 2019 10:45:14 -0700
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Subject: target/alpha: fix tlb_fill trap_arg2 value for instruction fetch
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Git-commit: cb1de55a83eaca9ee32be9c959dca99e11f2fea8
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Commit e41c94529740cc26 ("target/alpha: Convert to CPUClass::tlb_fill")
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slightly changed the way the trap_arg2 value is computed in case of TLB
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fill. The type of the variable used in the ternary operator has been
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changed from an int to an enum. This causes the -1 value to not be
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sign-extended to 64-bit in case of an instruction fetch. The trap_arg2
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ends up with 0xffffffff instead of 0xffffffffffffffff. Fix that by
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changing the -1 into -1LL.
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This fixes the execution of user space processes in qemu-system-alpha.
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Fixes: e41c94529740cc26
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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[rth: Test MMU_DATA_LOAD and MMU_DATA_STORE instead of implying them.]
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/alpha/helper.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/alpha/helper.c b/target/alpha/helper.c
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index 93b8e788b185f8b199b71256e5ff..d0cc6231925c932c192640632658 100644
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--- a/target/alpha/helper.c
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+++ b/target/alpha/helper.c
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@@ -283,7 +283,9 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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cs->exception_index = EXCP_MMFAULT;
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env->trap_arg0 = addr;
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env->trap_arg1 = fail;
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- env->trap_arg2 = (access_type == MMU_INST_FETCH ? -1 : access_type);
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+ env->trap_arg2 = (access_type == MMU_DATA_LOAD ? 0ull :
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+ access_type == MMU_DATA_STORE ? 1ull :
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+ /* access_type == MMU_INST_FETCH */ -1ull);
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cpu_loop_exit_restore(cs, retaddr);
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}
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