From 99aaadeae3b73ce65b3695a9fcae454ac09db81d Mon Sep 17 00:00:00 2001 From: Henry Wertz Date: Tue, 17 Apr 2018 12:06:23 -1000 Subject: [PATCH] tcg/arm: Fix memory barrier encoding I found with qemu 2.11.x or newer that I would get an illegal instruction error running some Intel binaries on my ARM chromebook. On investigation, I found it was quitting on memory barriers. qemu instruction: mb $0x31 was translating as: 0x604050cc: 5bf07ff5 blpl #0x600250a8 After patch it gives: 0x604050cc: f57ff05b dmb ish In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be correct based on online docs, but due to some endian-related shenanigans it had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier for ARMv6) also should be byte swapped (and this patch does so). I have not checked for correctness of aarch64's barrier instruction. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Henry Wertz Signed-off-by: Richard Henderson (cherry picked from commit 3f814b803797c007abfe5c4041de754e01723031) Signed-off-by: Bruce Rogers --- tcg/arm/tcg-target.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index dc83f3e5be..56a32a470f 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -159,8 +159,8 @@ typedef enum { INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, - INSN_DMB_ISH = 0x5bf07ff5, - INSN_DMB_MCR = 0xba0f07ee, + INSN_DMB_ISH = 0xf57ff05b, + INSN_DMB_MCR = 0xee070fba, /* Architected nop introduced in v6k. */ /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this