12286f39d2
- Include upstream patches designated as stable material and reviewed for applicability to include here. NOTE that the PIIX4 patch has migration implications: the change will also be applied to the SLE-15-SP2 qemu, and a live migration from that version to this SLE-15-SP3 qemu would require this patch to be applied for a successful migration if PIIX4 southbridge is used in the machine emulation (x86 i440fx) block-rbd-fix-memory-leak-in-qemu_rbd_co.patch block-rbd-Fix-memory-leak-in-qemu_rbd_co.patch cpu-core-Fix-help-of-CPU-core-device-typ.patch hw-arm-virt-acpi-build-Fix-GSIV-values-o.patch hw-block-fdc-Fix-fallback-property-on-sy.patch hw-isa-Kconfig-Add-missing-dependency-VI.patch hw-isa-piix4-Migrate-Reset-Control-Regis.patch hw-virtio-pci-Added-AER-capability.patch hw-virtio-pci-Added-counter-for-pcie-cap.patch s390x-css-report-errors-from-ccw_dstream.patch target-xtensa-fix-meson.build-rule-for-x.patch util-fix-use-after-free-in-module_load_o.patch virtio-pci-compat-page-aligned-ATS.patch OBS-URL: https://build.opensuse.org/request/show/885459 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=634
42 lines
1.5 KiB
Diff
42 lines
1.5 KiB
Diff
From: Andrew Melnychenko <andrew@daynix.com>
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Date: Thu, 3 Dec 2020 13:07:12 +0200
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Subject: hw/virtio-pci Added counter for pcie capabilities offsets.
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Git-commit: 06e97442420b03a1e0ff05e8eb554fac684ca736
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Removed hardcoded offset for ats. Added cap offset counter
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for future capabilities like AER.
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Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
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Message-Id: <20201203110713.204938-2-andrew@daynix.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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[BR: needed for stable commit d83f46d189a26fa32434139954d264326f199a45]
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---
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hw/virtio/virtio-pci.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
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index 36524a5728e40da961b4db862558..ceaa233129c529b604f461e45336 100644
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--- a/hw/virtio/virtio-pci.c
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+++ b/hw/virtio/virtio-pci.c
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@@ -1798,6 +1798,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
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if (pcie_port && pci_is_express(pci_dev)) {
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int pos;
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+ uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE;
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pos = pcie_endpoint_cap_init(pci_dev, 0);
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assert(pos > 0);
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@@ -1833,7 +1834,8 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
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}
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if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
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- pcie_ats_init(pci_dev, 256);
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+ pcie_ats_init(pci_dev, last_pcie_cap_offset);
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+ last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;
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}
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if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
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