a8263c0693
- Include upstream patches designated as stable material and reviewed for applicability to include here block-Separate-blk_is_writable-and-blk_s.patch hw-intc-arm_gic-Fix-interrupt-ID-in-GICD.patch hw-net-lan9118-Fix-RX-Status-FIFO-PEEK-v.patch hw-timer-slavio_timer-Allow-64-bit-acces.patch net-Fix-handling-of-id-in-netdev_add-and.patch target-arm-Don-t-decode-insns-in-the-XSc.patch target-arm-Fix-MTE0_ACTIVE.patch target-arm-Introduce-PREDDESC-field-defi.patch target-arm-Update-PFIRST-PNEXT-for-pred_.patch target-arm-Update-REV-PUNPK-for-pred_des.patch target-arm-Update-ZIP-UZP-TRN-for-pred_d.patch tcg-Use-memset-for-large-vector-byte-rep.patch ui-vnc-Add-missing-lock-for-send_color_m.patch virtio-move-use-disabled-flag-property-t.patch - binutils v2.36 has changed the handling of the assembler's -mx86-used-note, resulting in a build failure. To compensate, we now explicitly specify -mx86-used-note=no in the seabios Makefile (boo#1181775) build-be-explicit-about-mx86-used-note-n.patch OBS-URL: https://build.opensuse.org/request/show/869843 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=614
92 lines
3.9 KiB
Diff
92 lines
3.9 KiB
Diff
From: Richard Henderson <richard.henderson@linaro.org>
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Date: Tue, 12 Jan 2021 20:26:49 -1000
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Subject: target/arm: Update ZIP, UZP, TRN for pred_desc
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Git-commit: f9b0fcceccfc05cde62ff7577fbf2bc13b842414
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Update all users of do_perm_pred3 for the new
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predicate descriptor field definitions.
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20210113062650.593824-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/arm/sve_helper.c | 18 +++++++++---------
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target/arm/translate-sve.c | 12 ++++--------
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2 files changed, 13 insertions(+), 17 deletions(-)
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diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
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index ff01851bf288009ec3e7585b8e03..7eec4b6b73a273ecaf2fc218d8d4 100644
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--- a/target/arm/sve_helper.c
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+++ b/target/arm/sve_helper.c
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@@ -1868,9 +1868,9 @@ static uint64_t compress_bits(uint64_t x, int n)
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void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
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{
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- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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- int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
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- intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
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+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
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+ int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
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+ intptr_t high = FIELD_EX32(pred_desc, PREDDESC, DATA);
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uint64_t *d = vd;
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intptr_t i;
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@@ -1929,9 +1929,9 @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
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void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
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{
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- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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- int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
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- int odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1) << esz;
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+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
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+ int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
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+ int odd = FIELD_EX32(pred_desc, PREDDESC, DATA) << esz;
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uint64_t *d = vd, *n = vn, *m = vm;
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uint64_t l, h;
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intptr_t i;
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@@ -1986,9 +1986,9 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
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void HELPER(sve_trn_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
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{
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- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
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- uintptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
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- bool odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
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+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
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+ int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
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+ int odd = FIELD_EX32(pred_desc, PREDDESC, DATA);
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uint64_t *d = vd, *n = vn, *m = vm;
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uint64_t mask;
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int shr, shl;
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diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
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index efcb646f729b1dbe4f7989e2fb9d..0baca176a090001de915a7866af4 100644
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--- a/target/arm/translate-sve.c
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+++ b/target/arm/translate-sve.c
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@@ -2110,19 +2110,15 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd,
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unsigned vsz = pred_full_reg_size(s);
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- /* Predicate sizes may be smaller and cannot use simd_desc.
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- We cannot round up, as we do elsewhere, because we need
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- the exact size for ZIP2 and REV. We retain the style for
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- the other helpers for consistency. */
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TCGv_ptr t_d = tcg_temp_new_ptr();
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TCGv_ptr t_n = tcg_temp_new_ptr();
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TCGv_ptr t_m = tcg_temp_new_ptr();
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TCGv_i32 t_desc;
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- int desc;
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+ uint32_t desc = 0;
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- desc = vsz - 2;
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- desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz);
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- desc = deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd);
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+ desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
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+ desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
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+ desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
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tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
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tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
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