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qemu/0020-TCG-sync-op-32-bit-targets-fixed.patch
OBS User autobuild ae572d8970 Accepting request 1038 from GNOME:Factory
Copy from IBS home:uli_suse:branches:SUSE:Factory:Head/qemu based on submit request 1038 from user uli_suse

OBS-URL: https://build.opensuse.org/request/show/1038
OBS-URL: https://build.opensuse.org/package/show/openSUSE:Factory/qemu?expand=0&rev=31
2009-08-11 15:37:13 +00:00

83 lines
2.4 KiB
Diff

From 3d1745fd8e80e99b435b63b650b9b31202aace6c Mon Sep 17 00:00:00 2001
From: Ulrich Hecht <uli@suse.de>
Date: Fri, 24 Jul 2009 17:25:37 +0200
Subject: [PATCH 20/33] TCG "sync" op (32-bit targets fixed)
sync allows concurrent accesses to locations in memory through different TCG
variables. This comes in handy when you are emulating CPU registers that can
be used as either 32 or 64 bit, as TCG doesn't know anything about aliases.
See the s390x target for an example.
Fixed to not break 32-bit target builds.
Signed-off-by: Ulrich Hecht <uli@suse.de>
---
tcg/tcg-op.h | 12 ++++++++++++
tcg/tcg-opc.h | 2 ++
tcg/tcg.c | 6 ++++++
3 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index f3f2f71..6bcaf5b 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -316,6 +316,18 @@ static inline void tcg_gen_br(int label)
tcg_gen_op1i(INDEX_op_br, label);
}
+static inline void tcg_gen_sync_i32(TCGv_i32 arg)
+{
+ tcg_gen_op1_i32(INDEX_op_sync_i32, arg);
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static inline void tcg_gen_sync_i64(TCGv_i64 arg)
+{
+ tcg_gen_op1_i64(INDEX_op_sync_i64, arg);
+}
+#endif
+
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
{
if (!TCGV_EQUAL_I32(ret, arg))
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 3a095fc..654a45f 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -40,6 +40,7 @@ DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
+DEF2(sync_i32, 0, 1, 0, 0)
DEF2(mov_i32, 1, 1, 0, 0)
DEF2(movi_i32, 1, 0, 1, 0)
/* load/store */
@@ -103,6 +104,7 @@ DEF2(neg_i32, 1, 1, 0, 0)
#endif
#if TCG_TARGET_REG_BITS == 64
+DEF2(sync_i64, 0, 1, 0, 0)
DEF2(mov_i64, 1, 1, 0, 0)
DEF2(movi_i64, 1, 0, 1, 0)
/* load/store */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 299bff6..86e16fa 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1927,6 +1927,12 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
// dump_regs(s);
#endif
switch(opc) {
+ case INDEX_op_sync_i32:
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_sync_i64:
+#endif
+ temp_save(s, args[0], s->reserved_regs);
+ break;
case INDEX_op_mov_i32:
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_mov_i64:
--
1.6.2.1