d665afae2a
A couple of fixes, including one which gives confidence we can submit to Factory finally. OBS-URL: https://build.opensuse.org/request/show/612290 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=410
49 lines
1.8 KiB
Diff
49 lines
1.8 KiB
Diff
From 99aaadeae3b73ce65b3695a9fcae454ac09db81d Mon Sep 17 00:00:00 2001
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From: Henry Wertz <hwertz10@gmail.com>
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Date: Tue, 17 Apr 2018 12:06:23 -1000
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Subject: [PATCH] tcg/arm: Fix memory barrier encoding
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I found with qemu 2.11.x or newer that I would get an illegal instruction
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error running some Intel binaries on my ARM chromebook. On investigation,
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I found it was quitting on memory barriers.
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qemu instruction:
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mb $0x31
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was translating as:
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0x604050cc: 5bf07ff5 blpl #0x600250a8
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After patch it gives:
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0x604050cc: f57ff05b dmb ish
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In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be
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correct based on online docs, but due to some endian-related shenanigans it
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had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory
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barrier for ARMv6) also should be byte swapped (and this patch does so).
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I have not checked for correctness of aarch64's barrier instruction.
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Cc: qemu-stable@nongnu.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Henry Wertz <hwertz10@gmail.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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(cherry picked from commit 3f814b803797c007abfe5c4041de754e01723031)
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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tcg/arm/tcg-target.inc.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
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index dc83f3e5be..56a32a470f 100644
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--- a/tcg/arm/tcg-target.inc.c
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+++ b/tcg/arm/tcg-target.inc.c
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@@ -159,8 +159,8 @@ typedef enum {
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INSN_STRD_IMM = 0x004000f0,
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INSN_STRD_REG = 0x000000f0,
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- INSN_DMB_ISH = 0x5bf07ff5,
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- INSN_DMB_MCR = 0xba0f07ee,
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+ INSN_DMB_ISH = 0xf57ff05b,
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+ INSN_DMB_MCR = 0xee070fba,
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/* Architected nop introduced in v6k. */
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/* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
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