e5bf87c674
Address recent cpu vulnerability code named Spectre, as far as QEMU is concerned. (CVE-2017-5715 bsc#1068032) OBS-URL: https://build.opensuse.org/request/show/561702 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=381
161 lines
5.5 KiB
Diff
161 lines
5.5 KiB
Diff
From 5db61cfacabb4d9b385a2c7a4d7a7a9e25e0a91a Mon Sep 17 00:00:00 2001
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From: Wei Wang <wei.w.wang@intel.com>
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Date: Tue, 7 Nov 2017 16:39:49 +0800
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Subject: [PATCH] i386/kvm: MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD
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CPUID(EAX=0X7,ECX=0).EDX[26]/[27] indicates the support of
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MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD. Expose the CPUID
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to the guest. Also add the support of transferring the MSRs during live
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migration.
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Signed-off-by: Wei Wang <wei.w.wang@intel.com>
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[BR: BSC#1068032 CVE-2017-5715]
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/i386/cpu.c | 3 ++-
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target/i386/cpu.h | 4 ++++
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target/i386/kvm.c | 14 +++++++++++++-
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target/i386/machine.c | 20 ++++++++++++++++++++
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4 files changed, 39 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 045d66191f..4a403b1e7b 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -2880,13 +2880,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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case 7:
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/* Structured Extended Feature Flags Enumeration Leaf */
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if (count == 0) {
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+ host_cpuid(index, 0, eax, ebx, ecx, edx);
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*eax = 0; /* Maximum ECX value for sub-leaves */
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*ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
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*ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
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if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
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*ecx |= CPUID_7_0_ECX_OSPKE;
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}
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- *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
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+ *edx = env->features[FEAT_7_0_EDX] | *edx;
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} else {
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*eax = 0;
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*ebx = 0;
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index cbdd631e2e..d9ecf7a368 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -335,6 +335,7 @@
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#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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#define MSR_TSC_ADJUST 0x0000003b
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+#define MSR_IA32_SPEC_CTRL 0x00000048
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#define MSR_IA32_TSCDEADLINE 0x6e0
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#define FEATURE_CONTROL_LOCKED (1<<0)
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@@ -641,6 +642,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
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+#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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+#define CPUID_7_0_EDX_PRED_CMD (1U << 27)
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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@@ -1183,6 +1186,7 @@ typedef struct CPUX86State {
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uint64_t xss;
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+ uint64_t spec_ctrl;
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TPRAccess tpr_access_type;
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} CPUX86State;
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diff --git a/target/i386/kvm.c b/target/i386/kvm.c
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index b1e32e95d3..d0041e6285 100644
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--- a/target/i386/kvm.c
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+++ b/target/i386/kvm.c
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@@ -76,6 +76,7 @@ static bool has_msr_star;
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static bool has_msr_hsave_pa;
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static bool has_msr_tsc_aux;
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static bool has_msr_tsc_adjust;
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+static bool has_msr_spec_ctrl;
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static bool has_msr_tsc_deadline;
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static bool has_msr_feature_control;
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static bool has_msr_misc_enable;
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@@ -1108,6 +1109,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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case MSR_TSC_ADJUST:
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has_msr_tsc_adjust = true;
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break;
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+ case MSR_IA32_SPEC_CTRL:
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+ has_msr_spec_ctrl = true;
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+ break;
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case MSR_IA32_TSCDEADLINE:
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has_msr_tsc_deadline = true;
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break;
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@@ -1626,6 +1630,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_xss) {
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kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
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}
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+ if (has_msr_spec_ctrl) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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+ }
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#ifdef TARGET_X86_64
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if (lm_capable_kernel) {
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kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
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@@ -1998,7 +2005,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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if (has_msr_xss) {
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kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
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}
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-
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+ if (has_msr_spec_ctrl) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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+ }
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if (!env->tsc_valid) {
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kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
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@@ -2220,6 +2229,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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case MSR_IA32_XSS:
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env->xss = msrs[i].data;
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break;
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+ case MSR_IA32_SPEC_CTRL:
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+ env->spec_ctrl = msrs[i].data;
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+ break;
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default:
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if (msrs[i].index >= MSR_MC0_CTL &&
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msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
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diff --git a/target/i386/machine.c b/target/i386/machine.c
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index df5ec359eb..d561a65153 100644
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--- a/target/i386/machine.c
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+++ b/target/i386/machine.c
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@@ -759,6 +759,25 @@ static const VMStateDescription vmstate_xss = {
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}
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};
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+static bool spec_ctrl_needed(void *opaque)
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+{
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+ X86CPU *cpu = opaque;
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+ CPUX86State *env = &cpu->env;
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+
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+ return env->spec_ctrl != 0;
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+}
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+
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+static const VMStateDescription vmstate_spec_ctrl = {
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+ .name = "cpu/spec_ctrl",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .needed = spec_ctrl_needed,
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+ .fields = (VMStateField[]) {
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+ VMSTATE_UINT64(env.spec_ctrl, X86CPU),
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+ VMSTATE_END_OF_LIST()
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+ }
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+};
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+
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#ifdef TARGET_X86_64
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static bool pkru_needed(void *opaque)
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{
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@@ -932,6 +951,7 @@ VMStateDescription vmstate_x86_cpu = {
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&vmstate_msr_hyperv_stimer,
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&vmstate_avx512,
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&vmstate_xss,
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+ &vmstate_spec_ctrl,
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&vmstate_tsc_khz,
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#ifdef TARGET_X86_64
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&vmstate_pkru,
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