SHA256
1
0
forked from pool/qemu
qemu/qemu-cvs-ppcspe.patch

34 lines
987 B
Diff

--- target-ppc/op.c
+++ target-ppc/op.c
@@ -2720,6 +2720,7 @@
}
#endif /* !defined(CONFIG_USER_ONLY) */
+#if defined(TARGET_PPC64)
/* SPE extension */
void OPPROTO op_splatw_T1_64 (void)
{
@@ -3438,3 +3439,4 @@
T0 = _do_efdtsteq(T0_64, T1_64);
RETURN();
}
+#endif
--- target-ppc/translate.c
+++ target-ppc/translate.c
@@ -5853,6 +5853,7 @@
#endif /* !defined(TARGET_PPC64) */
+#if defined(TARGET_PPC64)
#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
{ \
@@ -6760,6 +6761,7 @@
GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
+#endif
/* End opcode list */
GEN_OPCODE_MARK(end);