From 529744c22f85217a71846ce0a4429996574c3aa3c6d6f2a9a9e59a855076ac69 Mon Sep 17 00:00:00 2001 From: Guillaume GARDET Date: Mon, 11 May 2020 14:24:02 +0000 Subject: [PATCH] Accepting request 802701 from hardware:boot:staging OBS-URL: https://build.opensuse.org/request/show/802701 OBS-URL: https://build.opensuse.org/package/show/hardware:boot/u-boot?expand=0&rev=98 --- ...-usb-xhci-Add-missing-cache-flush-in.patch | 35 + ...-usb-xhci-Use-only-32-bit-accesses-i.patch | 62 ++ ...-pci-Move-some-PCIe-register-offset-.patch | 79 +++ ...-rpi4-shorten-a-mapping-for-the-DRAM.patch | 27 + ...-rpi4-add-a-mapping-for-the-PCIe-XHC.patch | 70 ++ ...-linux-bitfield.h-Add-primitives-for.patch | 77 +++ ...-pci-Add-some-PCI-Express-capability.patch | 38 ++ ...-pci-Add-driver-for-Broadcom-STB-PCI.patch | 646 ++++++++++++++++++ ...-config-Enable-support-for-the-XHCI-.patch | 138 ++++ ...-arm-rpi-Add-function-to-trigger-VL8.patch | 117 ++++ ...-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch | 85 +++ ...-config-Enable-USB-Keyboard-support-.patch | 40 ++ u-boot.changes | 19 + u-boot.spec | 12 + 14 files changed, 1445 insertions(+) create mode 100644 0014-usb-xhci-Add-missing-cache-flush-in.patch create mode 100644 0015-usb-xhci-Use-only-32-bit-accesses-i.patch create mode 100644 0016-pci-Move-some-PCIe-register-offset-.patch create mode 100644 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch create mode 100644 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch create mode 100644 0019-linux-bitfield.h-Add-primitives-for.patch create mode 100644 0020-pci-Add-some-PCI-Express-capability.patch create mode 100644 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch create mode 100644 0022-config-Enable-support-for-the-XHCI-.patch create mode 100644 0023-arm-rpi-Add-function-to-trigger-VL8.patch create mode 100644 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch create mode 100644 0025-config-Enable-USB-Keyboard-support-.patch diff --git a/0014-usb-xhci-Add-missing-cache-flush-in.patch b/0014-usb-xhci-Add-missing-cache-flush-in.patch new file mode 100644 index 0000000..5a51849 --- /dev/null +++ b/0014-usb-xhci-Add-missing-cache-flush-in.patch @@ -0,0 +1,35 @@ +From 96a515925eddcb28645391a0605710cfa79e7351 Mon Sep 17 00:00:00 2001 +From: Sylwester Nawrocki +Date: Mon, 4 May 2020 14:45:14 +0200 +Subject: [PATCH] usb: xhci: Add missing cache flush in the scratchpad array + initialization + +In current code there is no cache flush after initializing the scratchpad +buffer array with the scratchpad buffer pointers. This leads to a failure +of the "slot enable" command on the rpi4 board (Broadcom STB PCIe +controller + VL805 USB hub) - the very first TRB transfer on the command +ring fails and there is a timeout while waiting for the command completion +event. After adding the missing cache flush everything seems to be working +as expected. + +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +Reviewed-by: Nicolas Saenz Julienne +--- + drivers/usb/host/xhci-mem.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 93450ee3b7..729bdc3c84 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) + scratchpad->sp_array[i] = cpu_to_le64(ptr); + } + ++ xhci_flush_cache((uintptr_t)scratchpad->sp_array, ++ sizeof(u64) * num_sp); ++ + return 0; + + fail_sp3: diff --git a/0015-usb-xhci-Use-only-32-bit-accesses-i.patch b/0015-usb-xhci-Use-only-32-bit-accesses-i.patch new file mode 100644 index 0000000..5507952 --- /dev/null +++ b/0015-usb-xhci-Use-only-32-bit-accesses-i.patch @@ -0,0 +1,62 @@ +From 919357cfab0b8a07184b676b50c3a31582e3dcdc Mon Sep 17 00:00:00 2001 +From: Sylwester Nawrocki +Date: Mon, 4 May 2020 14:45:15 +0200 +Subject: [PATCH] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq + +There might be hardware configurations where 64-bit data accesses +to XHCI registers are not supported properly. This patch removes +the readq/writeq so always two 32-bit accesses are used to read/write +64-bit XHCI registers, similarly as it is done in Linux kernel. + +This patch fixes operation of the XHCI controller on RPI4 Broadcom +BCM2711 SoC based board, where the VL805 USB XHCI controller is +connected to the PCIe Root Complex, which is attached to the system +through the SCB bridge. + +Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely +the 64-bit wide register accesses initiated by the CPU are not properly +translated to a sequence of 32-bit PCIe accesses. +xhci_readq(), for example, always returns same value in upper and lower +32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. + +Cc: Sergey Temerkhanov +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +Reviewed-by: Nicolas Saenz Julienne +--- + include/usb/xhci.h | 8 -------- + 1 file changed, 8 deletions(-) + +diff --git a/include/usb/xhci.h b/include/usb/xhci.h +index 6017504488..c16106a2fc 100644 +--- a/include/usb/xhci.h ++++ b/include/usb/xhci.h +@@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) + */ + static inline u64 xhci_readq(__le64 volatile *regs) + { +-#if BITS_PER_LONG == 64 +- return readq(regs); +-#else + __u32 *ptr = (__u32 *)regs; + u64 val_lo = readl(ptr); + u64 val_hi = readl(ptr + 1); + return val_lo + (val_hi << 32); +-#endif + } + + static inline void xhci_writeq(__le64 volatile *regs, const u64 val) + { +-#if BITS_PER_LONG == 64 +- writeq(val, regs); +-#else + __u32 *ptr = (__u32 *)regs; + u32 val_lo = lower_32_bits(val); + /* FIXME */ + u32 val_hi = upper_32_bits(val); + writel(val_lo, ptr); + writel(val_hi, ptr + 1); +-#endif + } + + int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, diff --git a/0016-pci-Move-some-PCIe-register-offset-.patch b/0016-pci-Move-some-PCIe-register-offset-.patch new file mode 100644 index 0000000..d4eb737 --- /dev/null +++ b/0016-pci-Move-some-PCIe-register-offset-.patch @@ -0,0 +1,79 @@ +From 18844a477d00a24fdeff913c4c277d53ee98094d Mon Sep 17 00:00:00 2001 +From: Sylwester Nawrocki +Date: Mon, 4 May 2020 14:45:16 +0200 +Subject: [PATCH] pci: Move some PCIe register offset definitions to a common + header + +Some PCI Express register offsets are currently defined in multiple +drivers, move them to a common header to avoid re-definitions and +as a pre-requisite for adding new PCIe driver. +While at it replace some spaces with tabs. + +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +Reviewed-by: Nicolas Saenz Julienne +--- + drivers/pci/pci-rcar-gen3.c | 8 -------- + drivers/pci/pcie_intel_fpga.c | 3 --- + include/pci.h | 13 +++++++++++-- + 3 files changed, 11 insertions(+), 13 deletions(-) + +diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c +index 30eff67dca..393f1c9ca9 100644 +--- a/drivers/pci/pci-rcar-gen3.c ++++ b/drivers/pci/pci-rcar-gen3.c +@@ -117,14 +117,6 @@ + #define RCAR_PCI_MAX_RESOURCES 4 + #define MAX_NR_INBOUND_MAPS 6 + +-#define PCI_EXP_FLAGS 2 /* Capabilities register */ +-#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +-#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +-#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +-#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +-#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +- + enum { + RCAR_PCI_ACCESS_READ, + RCAR_PCI_ACCESS_WRITE, +diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c +index 6a9f29c5c8..69363a077a 100644 +--- a/drivers/pci/pcie_intel_fpga.c ++++ b/drivers/pci/pcie_intel_fpga.c +@@ -65,9 +65,6 @@ + #define IS_ROOT_PORT(pcie, bdf) \ + ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) + +-#define PCI_EXP_LNKSTA 18 /* Link Status */ +-#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +- + /** + * struct intel_fpga_pcie - Intel FPGA PCIe controller state + * @bus: Pointer to the PCI bus +diff --git a/include/pci.h b/include/pci.h +index 174ddd4460..5bf91a43af 100644 +--- a/include/pci.h ++++ b/include/pci.h +@@ -471,10 +471,19 @@ + #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ + + /* PCI Express capabilities */ ++#define PCI_EXP_FLAGS 2 /* Capabilities register */ ++#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ ++#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ + #define PCI_EXP_DEVCAP 4 /* Device capabilities */ +-#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ ++#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ + #define PCI_EXP_DEVCTL 8 /* Device Control */ +-#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ ++#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ ++#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ ++#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ ++#define PCI_EXP_LNKSTA 18 /* Link Status */ ++#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ ++#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ ++#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ + + /* Include the ID list */ + diff --git a/0017-rpi4-shorten-a-mapping-for-the-DRAM.patch b/0017-rpi4-shorten-a-mapping-for-the-DRAM.patch new file mode 100644 index 0000000..de22373 --- /dev/null +++ b/0017-rpi4-shorten-a-mapping-for-the-DRAM.patch @@ -0,0 +1,27 @@ +From 4db83106c1da071b0e4ee56675bdbf448f2961fc Mon Sep 17 00:00:00 2001 +From: Marek Szyprowski +Date: Mon, 4 May 2020 14:45:17 +0200 +Subject: [PATCH] rpi4: shorten a mapping for the DRAM + +Remove the overlap between DRAM and device's IO area. + +Signed-off-by: Marek Szyprowski +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Nicolas Saenz Julienne +--- + arch/arm/mach-bcm283x/init.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index 9966d6c833..42953561a7 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, +- .size = 0xfe000000UL, ++ .size = 0xfc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { diff --git a/0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch b/0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch new file mode 100644 index 0000000..77a5d1b --- /dev/null +++ b/0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch @@ -0,0 +1,70 @@ +From c64da6a3c2950b925e95fb892e381ce89a869c8e Mon Sep 17 00:00:00 2001 +From: Marek Szyprowski +Date: Mon, 4 May 2020 14:45:18 +0200 +Subject: [PATCH] rpi4: add a mapping for the PCIe XHCI controller MMIO + registers (ARM 64bit) + +Create a non-cacheable mapping for the 0x600000000 physical memory region, +where MMIO registers for the PCIe XHCI controller are instantiated by the +PCIe bridge. + +Signed-off-by: Marek Szyprowski +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Nicolas Saenz Julienne +--- + arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index 42953561a7..6a748da171 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -11,10 +11,15 @@ + #include + #include + ++#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL ++#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL ++ + #ifdef CONFIG_ARM64 + #include + +-static struct mm_region bcm283x_mem_map[] = { ++#define MAX_MAP_MAX_ENTRIES (4) ++ ++static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, +@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { + } + }; + +-static struct mm_region bcm2711_mem_map[] = { ++static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, +@@ -48,6 +53,13 @@ static struct mm_region bcm2711_mem_map[] = { + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { ++ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, ++ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, ++ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, +@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) + { + int i; + +- for (i = 0; i < 2; i++) { ++ for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) { + mem_map[i].virt = pd[i].virt; + mem_map[i].phys = pd[i].phys; + mem_map[i].size = pd[i].size; diff --git a/0019-linux-bitfield.h-Add-primitives-for.patch b/0019-linux-bitfield.h-Add-primitives-for.patch new file mode 100644 index 0000000..740276a --- /dev/null +++ b/0019-linux-bitfield.h-Add-primitives-for.patch @@ -0,0 +1,77 @@ +From 897da38f243dd23eeaa5e1103bbd9f7d47bc0f7f Mon Sep 17 00:00:00 2001 +From: Nicolas Saenz Julienne +Date: Mon, 4 May 2020 14:45:20 +0200 +Subject: [PATCH] linux/bitfield.h: Add primitives for manipulating bitfields + both in host- and fixed-endian + +Imports Al Viro's original Linux commit 00b0c9b82663a, which contains +an in depth explanation and two fixes from Johannes Berg: + e7d4a95da86e0 "bitfield: fix *_encode_bits()", + 37a3862e12382 "bitfield: add u8 helpers". + +Signed-off-by: Nicolas Saenz Julienne +[s.nawrocki: added empty lines between functions and macros] +Signed-off-by: Sylwester Nawrocki +--- + include/linux/bitfield.h | 50 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h +index 8b9d6fff00..7acba4c524 100644 +--- a/include/linux/bitfield.h ++++ b/include/linux/bitfield.h +@@ -103,4 +103,54 @@ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + ++extern void __compiletime_error("value doesn't fit into mask") ++__field_overflow(void); ++extern void __compiletime_error("bad bitfield mask") ++__bad_mask(void); ++static __always_inline u64 field_multiplier(u64 field) ++{ ++ if ((field | (field - 1)) & ((field | (field - 1)) + 1)) ++ __bad_mask(); ++ return field & -field; ++} ++static __always_inline u64 field_mask(u64 field) ++{ ++ return field / field_multiplier(field); ++} ++ ++#define ____MAKE_OP(type,base,to,from) \ ++static __always_inline __##type type##_encode_bits(base v, base field) \ ++{ \ ++ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ ++ __field_overflow(); \ ++ return to((v & field_mask(field)) * field_multiplier(field)); \ ++} \ ++static __always_inline __##type type##_replace_bits(__##type old, \ ++ base val, base field) \ ++{ \ ++ return (old & ~to(field)) | type##_encode_bits(val, field); \ ++} \ ++static __always_inline void type##p_replace_bits(__##type *p, \ ++ base val, base field) \ ++{ \ ++ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ ++} \ ++static __always_inline base type##_get_bits(__##type v, base field) \ ++{ \ ++ return (from(v) & field)/field_multiplier(field); \ ++} ++ ++#define __MAKE_OP(size) \ ++ ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ ++ ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ ++ ____MAKE_OP(u##size,u##size,,) ++ ++____MAKE_OP(u8,u8,,) ++__MAKE_OP(16) ++__MAKE_OP(32) ++__MAKE_OP(64) ++ ++#undef __MAKE_OP ++#undef ____MAKE_OP ++ + #endif diff --git a/0020-pci-Add-some-PCI-Express-capability.patch b/0020-pci-Add-some-PCI-Express-capability.patch new file mode 100644 index 0000000..c8cca6f --- /dev/null +++ b/0020-pci-Add-some-PCI-Express-capability.patch @@ -0,0 +1,38 @@ +From 278f85de3e80c3240448bb133af65520294ec590 Mon Sep 17 00:00:00 2001 +From: Sylwester Nawrocki +Date: Mon, 4 May 2020 14:45:21 +0200 +Subject: [PATCH] pci: Add some PCI Express capability register offset + definitions + +Add PCI Express capability definitions required by the Broadcom +STB PCIe controller driver. + +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +Reviewed-by: Nicolas Saenz Julienne +--- + include/pci.h | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/include/pci.h b/include/pci.h +index 5bf91a43af..5307478b44 100644 +--- a/include/pci.h ++++ b/include/pci.h +@@ -479,11 +479,17 @@ + #define PCI_EXP_DEVCTL 8 /* Device Control */ + #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ + #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ ++#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ ++#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ + #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ + #define PCI_EXP_LNKSTA 18 /* Link Status */ ++#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ ++#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ ++#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ + #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ + #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ + #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ ++#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ + + /* Include the ID list */ + diff --git a/0021-pci-Add-driver-for-Broadcom-STB-PCI.patch b/0021-pci-Add-driver-for-Broadcom-STB-PCI.patch new file mode 100644 index 0000000..22d0c65 --- /dev/null +++ b/0021-pci-Add-driver-for-Broadcom-STB-PCI.patch @@ -0,0 +1,646 @@ +From 04b021d3e62a886e243af767667abe76d1939db4 Mon Sep 17 00:00:00 2001 +From: Sylwester Nawrocki +Date: Mon, 4 May 2020 14:45:22 +0200 +Subject: [PATCH] pci: Add driver for Broadcom STB PCIe controller + +This patch adds basic driver for the Broadcom STB PCIe host controller. +The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI +handling removed. The inbound access memory region is not currently +parsed from dma-ranges DT property and a fixed 4GB region is used. + +The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 +USB Host Controller. + +Signed-off-by: Nicolas Saenz Julienne +Signed-off-by: Sylwester Nawrocki +--- + drivers/pci/Kconfig | 6 + + drivers/pci/Makefile | 1 + + drivers/pci/pcie_brcmstb.c | 594 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 601 insertions(+) + create mode 100644 drivers/pci/pcie_brcmstb.c + +diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig +index 437cd9a055..056a021194 100644 +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -197,4 +197,10 @@ config PCIE_MEDIATEK + Say Y here if you want to enable Gen2 PCIe controller, + which could be found on MT7623 SoC family. + ++config PCI_BRCMSTB ++ bool "Broadcom STB PCIe controller" ++ depends on DM_PCI ++ depends on ARCH_BCM283X ++ help ++ Say Y here if you want to enable Broadcom STB PCIe controller support. + endif +diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile +index c051ecc9f3..3e53b1f717 100644 +--- a/drivers/pci/Makefile ++++ b/drivers/pci/Makefile +@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o + obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o + obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o + obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o ++obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +new file mode 100644 +index 0000000000..d1d86bcab0 +--- /dev/null ++++ b/drivers/pci/pcie_brcmstb.c +@@ -0,0 +1,594 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom STB PCIe controller driver ++ * ++ * Copyright (C) 2020 Samsung Electronics Co., Ltd. ++ * ++ * Based on upstream Linux kernel driver: ++ * drivers/pci/controller/pcie-brcmstb.c ++ * Copyright (C) 2009 - 2017 Broadcom ++ * ++ * Based driver by Nicolas Saenz Julienne ++ * Copyright (C) 2020 Nicolas Saenz Julienne ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ ++#define BRCM_PCIE_CAP_REGS 0x00ac ++ ++/* Broadcom STB PCIe Register Offsets */ ++#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 ++#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc ++#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 ++ ++#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c ++#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff ++ ++#define PCIE_RC_DL_MDIO_ADDR 0x1100 ++#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 ++#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 ++ ++#define PCIE_MISC_MISC_CTRL 0x4008 ++#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 ++#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 ++#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 ++#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128 0x0 ++#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c ++#define PCIE_MEM_WIN0_LO(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 ++#define PCIE_MEM_WIN0_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) ++ ++#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c ++#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f ++ ++#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 ++#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f ++#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 ++ ++#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c ++#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f ++ ++#define PCIE_MISC_PCIE_STATUS 0x4068 ++#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 ++#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 ++#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 ++#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 ++#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff ++#define PCIE_MEM_WIN0_BASE_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff ++#define PCIE_MEM_WIN0_LIMIT_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) ++ ++#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 ++#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 ++#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 ++ ++#define PCIE_MSI_INTR2_CLR 0x4508 ++#define PCIE_MSI_INTR2_MASK_SET 0x4510 ++ ++#define PCIE_EXT_CFG_DATA 0x8000 ++ ++#define PCIE_EXT_CFG_INDEX 0x9000 ++#define PCIE_EXT_BUSNUM_SHIFT 20 ++#define PCIE_EXT_SLOT_SHIFT 15 ++#define PCIE_EXT_FUNC_SHIFT 12 ++ ++#define PCIE_RGR1_SW_INIT_1 0x9210 ++#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 ++#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 ++ ++/* PCIe parameters */ ++#define BRCM_NUM_PCIE_OUT_WINS 0x4 ++ ++/* MDIO registers */ ++#define MDIO_PORT0 0x0 ++#define MDIO_DATA_MASK 0x7fffffff ++#define MDIO_PORT_MASK 0xf0000 ++#define MDIO_REGAD_MASK 0xffff ++#define MDIO_CMD_MASK 0xfff00000 ++#define MDIO_CMD_READ 0x1 ++#define MDIO_CMD_WRITE 0x0 ++#define MDIO_DATA_DONE_MASK 0x80000000 ++#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) ++#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) ++#define SSC_REGS_ADDR 0x1100 ++#define SET_ADDR_OFFSET 0x1f ++#define SSC_CNTL_OFFSET 0x2 ++#define SSC_CNTL_OVRD_EN_MASK 0x8000 ++#define SSC_CNTL_OVRD_VAL_MASK 0x4000 ++#define SSC_STATUS_OFFSET 0x1 ++#define SSC_STATUS_SSC_MASK 0x400 ++#define SSC_STATUS_PLL_LOCK_MASK 0x800 ++ ++struct brcm_pcie { ++ void __iomem *base; ++ ++ int gen; ++ bool ssc; ++}; ++ ++#define msleep(a) udelay((a) * 1000) ++ ++/* ++ * This is to convert the size of the inbound "BAR" region to the ++ * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE ++ */ ++static int brcm_pcie_encode_ibar_size(u64 size) ++{ ++ int log2_in = ilog2(size); ++ ++ if (log2_in >= 12 && log2_in <= 15) ++ /* Covers 4KB to 32KB (inclusive) */ ++ return (log2_in - 12) + 0x1c; ++ else if (log2_in >= 16 && log2_in <= 37) ++ /* Covers 64KB to 32GB, (inclusive) */ ++ return log2_in - 15; ++ /* Something is awry so disable */ ++ return 0; ++} ++ ++/* Configuration space read/write support */ ++static inline int brcm_pcie_cfg_index(pci_dev_t bdf, int reg) ++{ ++ return (PCI_DEV(bdf) << PCIE_EXT_SLOT_SHIFT) ++ | (PCI_FUNC(bdf) << PCIE_EXT_FUNC_SHIFT) ++ | (PCI_BUS(bdf) << PCIE_EXT_BUSNUM_SHIFT) ++ | (reg & ~3); ++} ++ ++/* The controller is capable of serving in both RC and EP roles */ ++static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) ++{ ++ u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); ++ ++ return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val); ++} ++ ++static bool brcm_pcie_link_up(struct brcm_pcie *pcie) ++{ ++ u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); ++ u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val); ++ u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val); ++ ++ return dla && plu; ++} ++ ++static int brcm_pcie_config_address(struct udevice *udev, pci_dev_t bdf, ++ uint offset, void **paddress) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(udev); ++ unsigned int bus = PCI_BUS(bdf); ++ unsigned int dev = PCI_DEV(bdf); ++ int idx; ++ ++ /* ++ * Busses 0 (host PCIe bridge) and 1 (its immediate child) ++ * are limited to a single device each ++ */ ++ if ((bus == (udev->seq + 1)) && dev > 0) ++ return -ENODEV; ++ ++ /* Accesses to the RC go right to the RC registers if PCI device == 0 */ ++ if (bus == udev->seq) { ++ if (PCI_DEV(bdf)) ++ return -ENODEV; ++ ++ *paddress = pcie->base + offset; ++ return 0; ++ } ++ ++ /* For devices, write to the config space index register */ ++ idx = brcm_pcie_cfg_index(bdf, 0); ++ ++ writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); ++ *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; ++ ++ return 0; ++} ++ ++static int brcm_pcie_read_config(struct udevice *bus, pci_dev_t bdf, ++ uint offset, ulong *valuep, ++ enum pci_size_t size) ++{ ++ return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, ++ bdf, offset, valuep, size); ++} ++ ++static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, ++ uint offset, ulong value, ++ enum pci_size_t size) ++{ ++ return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, ++ bdf, offset, value, size); ++} ++ ++static const char *link_speed_to_str(unsigned int s) ++{ ++ static const char * const speed_str[] = { "??", "2.5", "5.0", "8.0" }; ++ ++ if (s >= ARRAY_SIZE(speed_str)) ++ s = 0; ++ ++ return speed_str[s]; ++} ++ ++static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) ++{ ++ u32 tmp; ++ ++ tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); ++ u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK); ++ writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); ++} ++ ++static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) ++{ ++ u32 tmp; ++ ++ tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); ++ u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); ++ writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); ++} ++ ++static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) ++{ ++ u32 pkt = 0; ++ ++ pkt |= FIELD_PREP(MDIO_PORT_MASK, port); ++ pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad); ++ pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd); ++ ++ return pkt; ++} ++ ++/* Negative return value indicates error */ ++static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) ++{ ++ int tries; ++ u32 data; ++ ++ writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ), ++ base + PCIE_RC_DL_MDIO_ADDR); ++ readl(base + PCIE_RC_DL_MDIO_ADDR); ++ ++ data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); ++ for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { ++ udelay(10); ++ data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); ++ } ++ ++ *val = FIELD_GET(MDIO_DATA_MASK, data); ++ return MDIO_RD_DONE(data) ? 0 : -EIO; ++} ++ ++/* Negative return value indicates error */ ++static int brcm_pcie_mdio_write(void __iomem *base, u8 port, ++ u8 regad, u16 wrdata) ++{ ++ int tries; ++ u32 data; ++ ++ writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE), ++ base + PCIE_RC_DL_MDIO_ADDR); ++ readl(base + PCIE_RC_DL_MDIO_ADDR); ++ writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); ++ ++ data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); ++ for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { ++ udelay(10); ++ data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); ++ } ++ ++ return MDIO_WT_DONE(data) ? 0 : -EIO; ++} ++ ++/* ++ * Configures device for Spread Spectrum Clocking (SSC) mode; negative ++ * return value indicates error. ++ */ ++static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) ++{ ++ void __iomem *base = pcie->base; ++ int pll, ssc; ++ int ret; ++ u32 tmp; ++ ++ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, ++ SSC_REGS_ADDR); ++ if (ret < 0) ++ return ret; ++ ++ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); ++ if (ret < 0) ++ return ret; ++ ++ u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); ++ u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); ++ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); ++ if (ret < 0) ++ return ret; ++ ++ udelay(1000); ++ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); ++ if (ret < 0) ++ return ret; ++ ++ ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); ++ pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp); ++ ++ return ssc && pll ? 0 : -EIO; ++} ++ ++/* Limits operation to a specific generation (1, 2, or 3) */ ++static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) ++{ ++ void __iomem *base = pcie->base; ++ ++ u16 lnkctl2 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); ++ u32 lnkcap = readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); ++ ++ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; ++ writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); ++ ++ lnkctl2 = (lnkctl2 & ~0xf) | gen; ++ writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); ++} ++ ++static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, ++ unsigned int win, u64 phys_addr, ++ u64 pcie_addr, u64 size) ++{ ++ void __iomem *base = pcie->base; ++ u32 phys_addr_mb_high, limit_addr_mb_high; ++ phys_addr_t phys_addr_mb, limit_addr_mb; ++ int high_addr_shift; ++ u32 tmp; ++ ++ /* Set the base of the pcie_addr window */ ++ writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win)); ++ writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win)); ++ ++ /* Write the addr base & limit lower bits (in MBs) */ ++ phys_addr_mb = phys_addr / SZ_1M; ++ limit_addr_mb = (phys_addr + size - 1) / SZ_1M; ++ ++ tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win)); ++ u32p_replace_bits(&tmp, phys_addr_mb, ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); ++ u32p_replace_bits(&tmp, limit_addr_mb, ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win)); ++ ++ /* Write the cpu & limit addr upper bits */ ++ high_addr_shift = PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT; ++ phys_addr_mb_high = phys_addr_mb >> high_addr_shift; ++ tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win)); ++ u32p_replace_bits(&tmp, phys_addr_mb_high, ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win)); ++ ++ limit_addr_mb_high = limit_addr_mb >> high_addr_shift; ++ tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win)); ++ u32p_replace_bits(&tmp, limit_addr_mb_high, ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); ++} ++ ++static int brcm_pcie_probe(struct udevice *dev) ++{ ++ struct udevice *ctlr = pci_get_controller(dev); ++ struct pci_controller *hose = dev_get_uclass_priv(ctlr); ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ void __iomem *base = pcie->base; ++ bool ssc_good = false; ++ int num_out_wins = 0; ++ u64 rc_bar2_offset, rc_bar2_size; ++ unsigned int scb_size_val; ++ int i, ret; ++ u16 nlw, cls, lnksta; ++ u32 tmp; ++ ++ /* Reset the bridge */ ++ brcm_pcie_bridge_sw_init_set(pcie, 1); ++ ++ udelay(150); ++ ++ /* Take the bridge out of reset */ ++ brcm_pcie_bridge_sw_init_set(pcie, 0); ++ ++ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); ++ tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; ++ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); ++ /* Wait for SerDes to be stable */ ++ udelay(150); ++ ++ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ ++ u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); ++ u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); ++ u32p_replace_bits(&tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128, ++ PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); ++ writel(tmp, base + PCIE_MISC_MISC_CTRL); ++ ++ /* ++ * TODO: When support for other SoCs than BCM2711 is added we may ++ * need to use the base address and size(s) provided in the dma-ranges ++ * property. ++ */ ++ rc_bar2_offset = 0; ++ rc_bar2_size = 0xc0000000; ++ ++ tmp = lower_32_bits(rc_bar2_offset); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), ++ PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); ++ writel(upper_32_bits(rc_bar2_offset), ++ base + PCIE_MISC_RC_BAR2_CONFIG_HI); ++ ++ scb_size_val = rc_bar2_size ? ++ ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ ++ tmp = readl(base + PCIE_MISC_MISC_CTRL); ++ u32p_replace_bits(&tmp, scb_size_val, ++ PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK); ++ writel(tmp, base + PCIE_MISC_MISC_CTRL); ++ ++ /* Disable the PCIe->GISB memory window (RC_BAR1) */ ++ tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); ++ tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; ++ writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); ++ ++ /* Disable the PCIe->SCB memory window (RC_BAR3) */ ++ tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); ++ tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; ++ writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); ++ ++ /* Mask all interrupts since we are not handling any yet */ ++ writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET); ++ ++ /* Clear any interrupts we find on boot */ ++ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); ++ ++ if (pcie->gen) ++ brcm_pcie_set_gen(pcie, pcie->gen); ++ ++ /* Unassert the fundamental reset */ ++ brcm_pcie_perst_set(pcie, 0); ++ ++ /* Give the RC/EP time to wake up, before trying to configure RC. ++ * Intermittently check status for link-up, up to a total of 100ms. ++ */ ++ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) ++ msleep(5); ++ ++ if (!brcm_pcie_link_up(pcie)) { ++ printf("PCIe BRCM: link down\n"); ++ return -ENODEV; ++ } ++ ++ if (!brcm_pcie_rc_mode(pcie)) { ++ printf("PCIe misconfigured; is in EP mode\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < hose->region_count; i++) { ++ struct pci_region *reg = &hose->regions[i]; ++ ++ if (reg->flags != PCI_REGION_MEM) ++ continue; ++ ++ if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) ++ return -EINVAL; ++ ++ brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start, ++ reg->bus_start, reg->size); ++ ++ num_out_wins++; ++ } ++ ++ /* ++ * For config space accesses on the RC, show the right class for ++ * a PCIe-PCIe bridge (the default setting is to be EP mode). ++ */ ++ tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3); ++ u32p_replace_bits(&tmp, 0x060400, ++ PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK); ++ writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3); ++ ++ if (pcie->ssc) { ++ ret = brcm_pcie_set_ssc(pcie); ++ if (ret == 0) ++ ssc_good = true; ++ else ++ printf("PCIe BRCM: failed attempt to enter SSC mode\n"); ++ } ++ ++ lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); ++ cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); ++ nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); ++ ++ printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), ++ nlw, ssc_good ? "(SSC)" : "(!SSC)"); ++ ++ /* PCIe->SCB endian mode for BAR */ ++ tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); ++ u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, ++ PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); ++ writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); ++ ++ /* ++ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 ++ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. ++ */ ++ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); ++ tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; ++ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); ++ ++ return 0; ++} ++ ++static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ ofnode dn = dev_ofnode(dev); ++ u32 max_link_speed; ++ int ret; ++ ++ /* Get the controller base address */ ++ pcie->base = dev_read_addr_ptr(dev); ++ if (!pcie->base) ++ return -EINVAL; ++ ++ pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); ++ ++ ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); ++ if (ret < 0 || max_link_speed > 4) ++ pcie->gen = 0; ++ else ++ pcie->gen = max_link_speed; ++ ++ return 0; ++} ++ ++static const struct dm_pci_ops brcm_pcie_ops = { ++ .read_config = brcm_pcie_read_config, ++ .write_config = brcm_pcie_write_config, ++}; ++ ++static const struct udevice_id brcm_pcie_ids[] = { ++ { .compatible = "brcm,bcm2711-pcie" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(pcie_brcm_base) = { ++ .name = "pcie_brcm", ++ .id = UCLASS_PCI, ++ .ops = &brcm_pcie_ops, ++ .of_match = brcm_pcie_ids, ++ .probe = brcm_pcie_probe, ++ .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, ++ .priv_auto_alloc_size = sizeof(struct brcm_pcie), ++}; diff --git a/0022-config-Enable-support-for-the-XHCI-.patch b/0022-config-Enable-support-for-the-XHCI-.patch new file mode 100644 index 0000000..b446b28 --- /dev/null +++ b/0022-config-Enable-support-for-the-XHCI-.patch @@ -0,0 +1,138 @@ +From 7c75345077bc8f04a6a736b8e960df9799de20ac Mon Sep 17 00:00:00 2001 +From: Marek Szyprowski +Date: Mon, 4 May 2020 14:45:23 +0200 +Subject: [PATCH] config: Enable support for the XHCI controller on RPI4 board + +This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI +and USB commands. To get it working one has to call the following commands: +"pci enum; usb start;", thus such commands have been added to the default +"preboot" environment variable. One has to update their environment if it +is already configured to get this feature working out of the box. + +Signed-off-by: Marek Szyprowski +Signed-off-by: Sylwester Nawrocki +--- + configs/rpi_4_32b_defconfig | 9 +++++++++ + configs/rpi_4_defconfig | 9 +++++++++ + configs/rpi_arm64_defconfig | 8 +++++++- + 3 files changed, 25 insertions(+), 1 deletion(-) + +diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig +index 72cda5d949..1315f7449f 100644 +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_INTERFACE="mmc" +@@ -28,6 +32,9 @@ CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +@@ -40,6 +47,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 + CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + CONFIG_USB_GADGET_DWC2_OTG=y + CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_DM_VIDEO=y + # CONFIG_VIDEO_BPP8 is not set + # CONFIG_VIDEO_BPP16 is not set +diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig +index 6d148dab07..5051b8812f 100644 +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_INTERFACE="mmc" +@@ -28,6 +32,9 @@ CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +@@ -40,6 +47,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 + CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + CONFIG_USB_GADGET_DWC2_OTG=y + CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_DM_VIDEO=y + # CONFIG_VIDEO_BPP8 is not set + # CONFIG_VIDEO_BPP16 is not set +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index fea86be8b0..f12d1e340c 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="usb start" ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y +@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set + CONFIG_USB=y + CONFIG_DM_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_USB_DWC2=y + CONFIG_USB_KEYBOARD=y + CONFIG_USB_HOST_ETHER=y diff --git a/0023-arm-rpi-Add-function-to-trigger-VL8.patch b/0023-arm-rpi-Add-function-to-trigger-VL8.patch new file mode 100644 index 0000000..d4e314a --- /dev/null +++ b/0023-arm-rpi-Add-function-to-trigger-VL8.patch @@ -0,0 +1,117 @@ +From 3f74d0b9505c8718bfea156599e35ca260975780 Mon Sep 17 00:00:00 2001 +From: Nicolas Saenz Julienne +Date: Tue, 5 May 2020 18:26:06 +0200 +Subject: [PATCH] arm: rpi: Add function to trigger VL805's firmware load + +On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware +may either be loaded directly from an EEPROM or, if not present, by the +SoC's VideCore (the SoC's co-processor). Introduce the function that +informs VideCore that VL805 may need its firmware loaded. + +Signed-off-by: Nicolas Saenz Julienne +--- + arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++ + arch/arm/mach-bcm283x/include/mach/msg.h | 7 ++++ + arch/arm/mach-bcm283x/msg.c | 45 +++++++++++++++++++++++ + 3 files changed, 65 insertions(+) + +diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h +index 60e226ce1d..2ae2d3d97c 100644 +--- a/arch/arm/mach-bcm283x/include/mach/mbox.h ++++ b/arch/arm/mach-bcm283x/include/mach/mbox.h +@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette { + } body; + }; + ++#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 ++ ++struct bcm2835_mbox_tag_pci_dev_addr { ++ struct bcm2835_mbox_tag_hdr tag_hdr; ++ union { ++ struct { ++ u32 dev_addr; ++ } req; ++ struct { ++ } resp; ++ } body; ++}; ++ + /* + * Pass a raw u32 message to the VC, and receive a raw u32 back. + * +diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h +index 4afb08631b..f5213dd0e0 100644 +--- a/arch/arm/mach-bcm283x/include/mach/msg.h ++++ b/arch/arm/mach-bcm283x/include/mach/msg.h +@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, + int pixel_order, int alpha_mode, ulong *fb_basep, + ulong *fb_sizep, int *pitchp); + ++/** ++ * bcm2711_notify_vl805_reset() - get vl805's firmware loaded ++ * ++ * @return 0 if OK, -EIO on error ++ */ ++int bcm2711_notify_vl805_reset(void); ++ + #endif +diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c +index 94b75283f8..f8ef531652 100644 +--- a/arch/arm/mach-bcm283x/msg.c ++++ b/arch/arm/mach-bcm283x/msg.c +@@ -40,6 +40,12 @@ struct msg_setup { + u32 end_tag; + }; + ++struct msg_notify_vl805_reset { ++ struct bcm2835_mbox_hdr hdr; ++ struct bcm2835_mbox_tag_pci_dev_addr dev_addr; ++ u32 end_tag; ++}; ++ + int bcm2835_power_on_module(u32 module) + { + ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1); +@@ -151,3 +157,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, + + return 0; + } ++ ++/* ++ * The Raspberry Pi 4 gets its USB functionality from VL805, a PCIe chip that ++ * implements xHCI. After a PCI reset, VL805's firmware may either be loaded ++ * directly from an EEPROM or, if not present, by the SoC's co-processor, ++ * VideoCore. RPi4's VideoCore OS contains both the non public firmware load ++ * logic and the VL805 firmware blob. This function triggers the aforementioned ++ * process. ++ */ ++int bcm2711_notify_vl805_reset(void) ++{ ++ ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset, ++ msg_notify_vl805_reset, 1); ++ int ret; ++ ++ BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset); ++ BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr, ++ NOTIFY_XHCI_RESET); ++ ++ /* ++ * The pci device address is expected like this: ++ * ++ * PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12 ++ * ++ * But since RPi4's PCIe setup is hardwired, we know the address in ++ * advance. ++ */ ++ msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000; ++ ++ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, ++ &msg_notify_vl805_reset->hdr); ++ if (ret) { ++ printf("bcm2711: Faild to load vl805's firmware, %d\n", ret); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ diff --git a/0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch b/0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch new file mode 100644 index 0000000..5910122 --- /dev/null +++ b/0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch @@ -0,0 +1,85 @@ +From e5fa3a00fbbe9b19f0fa76e0c497e9d5acf940d6 Mon Sep 17 00:00:00 2001 +From: Nicolas Saenz Julienne +Date: Tue, 5 May 2020 18:26:07 +0200 +Subject: [PATCH] usb: xhci: Load Raspberry Pi 4 VL805's firmware + +When needed, RPi4's co-processor (called VideoCore) has to be instructed +to load VL805's firmware (the chip providing xHCI support). VideCore's +firmware expects the board's PCIe bus to be already configured in order +for it to load the xHCI chip firmware. So we have to make sure this +happens in between the PCIe configuration and xHCI startup. + +Introduce a callback in xhci_pci_probe() to run this platform specific +routine. + +Signed-off-by: Nicolas Saenz Julienne +--- + board/raspberrypi/rpi/rpi.c | 6 ++++++ + drivers/usb/host/xhci-pci.c | 6 ++++++ + include/usb/xhci.h | 3 +++ + 3 files changed, 15 insertions(+) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index e367ba3092..dcaf45fbf2 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -494,3 +495,8 @@ int ft_board_setup(void *blob, bd_t *bd) + + return 0; + } ++ ++void xhci_pci_fixup(struct udevice *dev) ++{ ++ bcm2711_notify_vl805_reset(); ++} +diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c +index c1f60da541..1285dde1ef 100644 +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -11,6 +11,10 @@ + #include + #include + ++__weak void xhci_pci_fixup(struct udevice *dev) ++{ ++} ++ + static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, + struct xhci_hcor **ret_hcor) + { +@@ -40,6 +44,8 @@ static int xhci_pci_probe(struct udevice *dev) + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + ++ xhci_pci_fixup(dev); ++ + xhci_pci_init(dev, &hccr, &hcor); + + return xhci_register(dev, hccr, hcor); +diff --git a/include/usb/xhci.h b/include/usb/xhci.h +index c16106a2fc..57feed7603 100644 +--- a/include/usb/xhci.h ++++ b/include/usb/xhci.h +@@ -16,6 +16,7 @@ + #ifndef HOST_XHCI_H_ + #define HOST_XHCI_H_ + ++#include + #include + #include + #include +@@ -1281,4 +1282,6 @@ extern struct dm_usb_ops xhci_usb_ops; + + struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev); + ++extern void xhci_pci_fixup(struct udevice *dev); ++ + #endif /* HOST_XHCI_H_ */ diff --git a/0025-config-Enable-USB-Keyboard-support-.patch b/0025-config-Enable-USB-Keyboard-support-.patch new file mode 100644 index 0000000..8871d1f --- /dev/null +++ b/0025-config-Enable-USB-Keyboard-support-.patch @@ -0,0 +1,40 @@ +From 8ae0b68bf17266338e1b5a91cc987f8f2dcba1ab Mon Sep 17 00:00:00 2001 +From: Nicolas Saenz Julienne +Date: Tue, 5 May 2020 16:51:29 +0200 +Subject: [PATCH] config: Enable USB Keyboard support on RPi4 + +Supporting USB keyboards out of the box is both handy for development +and production. Notably if u-boot is used to boot into GRUB. + +Signed-off-by: Nicolas Saenz Julienne +Reviewed-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +--- + configs/rpi_4_32b_defconfig | 1 + + configs/rpi_4_defconfig | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig +index 1315f7449f..2c5539102e 100644 +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -49,6 +49,7 @@ CONFIG_USB_GADGET_DWC2_OTG=y + CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_PCI=y ++CONFIG_USB_KEYBOARD=y + CONFIG_DM_VIDEO=y + # CONFIG_VIDEO_BPP8 is not set + # CONFIG_VIDEO_BPP16 is not set +diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig +index 5051b8812f..6f34ae9fbd 100644 +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -49,6 +49,7 @@ CONFIG_USB_GADGET_DWC2_OTG=y + CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_PCI=y ++CONFIG_USB_KEYBOARD=y + CONFIG_DM_VIDEO=y + # CONFIG_VIDEO_BPP8 is not set + # CONFIG_VIDEO_BPP16 is not set diff --git a/u-boot.changes b/u-boot.changes index 16710a9..3af81b7 100644 --- a/u-boot.changes +++ b/u-boot.changes @@ -1,3 +1,22 @@ +------------------------------------------------------------------- +Mon May 11 13:40:32 UTC 2020 - Matthias Brugger + +- Enable USB and USB keyboard on RPi4: +Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.04 +* Patches added: + 0014-usb-xhci-Add-missing-cache-flush-in.patch + 0015-usb-xhci-Use-only-32-bit-accesses-i.patch + 0016-pci-Move-some-PCIe-register-offset-.patch + 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch + 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch + 0019-linux-bitfield.h-Add-primitives-for.patch + 0020-pci-Add-some-PCI-Express-capability.patch + 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch + 0022-config-Enable-support-for-the-XHCI-.patch + 0023-arm-rpi-Add-function-to-trigger-VL8.patch + 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch + 0025-config-Enable-USB-Keyboard-support-.patch + ------------------------------------------------------------------- Fri Apr 17 12:05:54 UTC 2020 - Guillaume GARDET diff --git a/u-boot.spec b/u-boot.spec index ed8e4a2..52644ba 100644 --- a/u-boot.spec +++ b/u-boot.spec @@ -216,6 +216,18 @@ Patch0010: 0010-configs-am335x_evm-disable-BTRFS.patch Patch0011: 0011-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch Patch0012: 0012-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch Patch0013: 0013-uboot-fs-btrfs-Fix-LZO-false-decomp.patch +Patch0014: 0014-usb-xhci-Add-missing-cache-flush-in.patch +Patch0015: 0015-usb-xhci-Use-only-32-bit-accesses-i.patch +Patch0016: 0016-pci-Move-some-PCIe-register-offset-.patch +Patch0017: 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch +Patch0018: 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch +Patch0019: 0019-linux-bitfield.h-Add-primitives-for.patch +Patch0020: 0020-pci-Add-some-PCI-Express-capability.patch +Patch0021: 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch +Patch0022: 0022-config-Enable-support-for-the-XHCI-.patch +Patch0023: 0023-arm-rpi-Add-function-to-trigger-VL8.patch +Patch0024: 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch +Patch0025: 0025-config-Enable-USB-Keyboard-support-.patch # Patches: end BuildRequires: bc BuildRequires: bison