From b06166e31cfc59ce598e85fcb2667195379873a4283d173f939caa211a5b9293 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Tue, 28 Jan 2020 11:55:57 +0000 Subject: [PATCH] revert to last accepted SR OBS-URL: https://build.opensuse.org/package/show/hardware:boot/u-boot?expand=0&rev=79 --- ...-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch | 861 ------------------ 0011-Kconfig-add-btrfs-to-distro-boot.patch | 26 - ...-configs-Re-sync-with-CONFIG_DISTRO_.patch | 88 -- ...-net-Add-support-for-Broadcom-GENETv.patch | 788 ---------------- ...-rpi4-Update-memory-map-to-accommoda.patch | 34 - ...-rpi4-Enable-GENET-Ethernet-controll.patch | 58 -- _multibuild | 1 - u-boot.changes | 15 - u-boot.spec | 8 +- update_git.sh | 2 +- 10 files changed, 2 insertions(+), 1879 deletions(-) delete mode 100644 0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch delete mode 100644 0011-Kconfig-add-btrfs-to-distro-boot.patch delete mode 100644 0012-configs-Re-sync-with-CONFIG_DISTRO_.patch delete mode 100644 0013-net-Add-support-for-Broadcom-GENETv.patch delete mode 100644 0014-rpi4-Update-memory-map-to-accommoda.patch delete mode 100644 0015-rpi4-Enable-GENET-Ethernet-controll.patch diff --git a/0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch b/0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch deleted file mode 100644 index a88cb7c..0000000 --- a/0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch +++ /dev/null @@ -1,861 +0,0 @@ -From 453c6c8a556e4afd480602802f1b10ee55abaa98 Mon Sep 17 00:00:00 2001 -From: Thierry Reding -Date: Mon, 15 Apr 2019 11:32:39 +0200 -Subject: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support - -v5: https://www.mail-archive.com/u-boot@lists.denx.de/msg322738.html -The Jetson Nano Developer Kit is a Tegra X1 based development board. It -is similar to Jetson TX1 but it is not pin compatible. It features 4 GB -of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot -used for storage. - -HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 -and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI -Ethernet controller provides onboard network connectivity. - -A 40-pin header on the board can be used to extend the capabilities and -exposed interfaces of the Jetson Nano. - -[Yousaf]: fix build. add fdtfile in environment. - -Signed-off-by: Thierry Reding -Signed-off-by: Matthias Brugger ---- - arch/arm/dts/Makefile | 3 +- - arch/arm/dts/tegra210-p3450-0000.dts | 135 +++++++++ - arch/arm/mach-tegra/tegra210/Kconfig | 7 + - board/nvidia/p3450-0000/Kconfig | 12 + - board/nvidia/p3450-0000/MAINTAINERS | 6 + - board/nvidia/p3450-0000/Makefile | 8 + - board/nvidia/p3450-0000/p3450-0000.c | 198 +++++++++++++ - .../p3450-0000/pinmux-config-p3450-0000.h | 265 ++++++++++++++++++ - configs/p3450-0000_defconfig | 55 ++++ - include/configs/p3450-0000.h | 37 +++ - include/configs/tegra-common-post.h | 4 - - 11 files changed, 725 insertions(+), 5 deletions(-) - create mode 100644 arch/arm/dts/tegra210-p3450-0000.dts - create mode 100644 board/nvidia/p3450-0000/Kconfig - create mode 100644 board/nvidia/p3450-0000/MAINTAINERS - create mode 100644 board/nvidia/p3450-0000/Makefile - create mode 100644 board/nvidia/p3450-0000/p3450-0000.c - create mode 100644 board/nvidia/p3450-0000/pinmux-config-p3450-0000.h - create mode 100644 configs/p3450-0000_defconfig - create mode 100644 include/configs/p3450-0000.h - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 0127a91a82..ae93b71660 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -179,7 +179,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ - tegra210-e2220-1170.dtb \ - tegra210-p2371-0000.dtb \ - tegra210-p2371-2180.dtb \ -- tegra210-p2571.dtb -+ tegra210-p2571.dtb \ -+ tegra210-p3450-0000.dtb - - dtb-$(CONFIG_ARCH_MVEBU) += \ - armada-3720-db.dtb \ -diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts -new file mode 100644 -index 0000000000..d45ee9afc0 ---- /dev/null -+++ b/arch/arm/dts/tegra210-p3450-0000.dts -@@ -0,0 +1,135 @@ -+/dts-v1/; -+ -+#include "tegra210.dtsi" -+ -+/ { -+ model = "NVIDIA Jetson Nano Developer Kit"; -+ compatible = "nvidia,p3450-0000", "nvidia,tegra210"; -+ -+ chosen { -+ stdout-path = &uarta; -+ }; -+ -+ aliases { -+ ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; -+ i2c0 = "/i2c@7000d000"; -+ i2c2 = "/i2c@7000c400"; -+ i2c3 = "/i2c@7000c500"; -+ i2c4 = "/i2c@7000c700"; -+ sdhci0 = "/sdhci@700b0000"; -+ spi0 = "/spi@70410000"; -+ usb0 = "/usb@7d000000"; -+ }; -+ -+ memory { -+ reg = <0x0 0x80000000 0x0 0xc0000000>; -+ }; -+ -+ pcie@1003000 { -+ status = "okay"; -+ -+ pci@1,0 { -+ status = "okay"; -+ }; -+ -+ pci@2,0 { -+ status = "okay"; -+ -+ ethernet@0,0 { -+ reg = <0x000000 0 0 0 0>; -+ local-mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+ }; -+ }; -+ -+ serial@70006000 { -+ status = "okay"; -+ }; -+ -+ padctl@7009f000 { -+ pinctrl-0 = <&padctl_default>; -+ pinctrl-names = "default"; -+ -+ padctl_default: pinmux { -+ xusb { -+ nvidia,lanes = "otg-1", "otg-2"; -+ nvidia,function = "xusb"; -+ nvidia,iddq = <0>; -+ }; -+ -+ usb3 { -+ nvidia,lanes = "pcie-5", "pcie-6"; -+ nvidia,function = "usb3"; -+ nvidia,iddq = <0>; -+ }; -+ -+ pcie-x1 { -+ nvidia,lanes = "pcie-0"; -+ nvidia,function = "pcie-x1"; -+ nvidia,iddq = <0>; -+ }; -+ -+ pcie-x4 { -+ nvidia,lanes = "pcie-1", "pcie-2", -+ "pcie-3", "pcie-4"; -+ nvidia,function = "pcie-x4"; -+ nvidia,iddq = <0>; -+ }; -+ -+ sata { -+ nvidia,lanes = "sata-0"; -+ nvidia,function = "sata"; -+ nvidia,iddq = <0>; -+ }; -+ }; -+ }; -+ -+ sdhci@700b0000 { -+ status = "okay"; -+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; -+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; -+ bus-width = <4>; -+ }; -+ -+ i2c@7000c400 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ i2c@7000c500 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ i2c@7000c700 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ i2c@7000d000 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ spi@70410000 { -+ status = "okay"; -+ }; -+ -+ usb@7d000000 { -+ status = "okay"; -+ dr_mode = "peripheral"; -+ }; -+ -+ clocks { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clk32k_in: clock@0 { -+ compatible = "fixed-clock"; -+ reg = <0>; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ }; -+ }; -+}; -diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig -index 3637473051..97ed8e05f4 100644 ---- a/arch/arm/mach-tegra/tegra210/Kconfig -+++ b/arch/arm/mach-tegra/tegra210/Kconfig -@@ -35,6 +35,12 @@ config TARGET_P2571 - help - P2571 is a P2530 married to a P1963 I/O board - -+config TARGET_P3450_0000 -+ bool "NVIDIA Jetson Nano Developer Kit" -+ select BOARD_LATE_INIT -+ help -+ P3450-0000 is a P3448 CPU board married to a P3449 I/O board. -+ - endchoice - - config SYS_SOC -@@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig" - source "board/nvidia/p2371-0000/Kconfig" - source "board/nvidia/p2371-2180/Kconfig" - source "board/nvidia/p2571/Kconfig" -+source "board/nvidia/p3450-0000/Kconfig" - - endif -diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig -new file mode 100644 -index 0000000000..7a08cd8867 ---- /dev/null -+++ b/board/nvidia/p3450-0000/Kconfig -@@ -0,0 +1,12 @@ -+if TARGET_P3450_0000 -+ -+config SYS_BOARD -+ default "p3450-0000" -+ -+config SYS_VENDOR -+ default "nvidia" -+ -+config SYS_CONFIG_NAME -+ default "p3450-0000" -+ -+endif -diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS -new file mode 100644 -index 0000000000..40700066bf ---- /dev/null -+++ b/board/nvidia/p3450-0000/MAINTAINERS -@@ -0,0 +1,6 @@ -+P3450-0000 BOARD -+M: Tom Warren -+S: Maintained -+F: board/nvidia/p3450-0000/ -+F: include/configs/p3450-0000.h -+F: configs/p3450-0000_defconfig -diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile -new file mode 100644 -index 0000000000..993c506d82 ---- /dev/null -+++ b/board/nvidia/p3450-0000/Makefile -@@ -0,0 +1,8 @@ -+# -+# (C) Copyright 2018 -+# NVIDIA Corporation -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += p3450-0000.o -diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c -new file mode 100644 -index 0000000000..c7aa76a14e ---- /dev/null -+++ b/board/nvidia/p3450-0000/p3450-0000.c -@@ -0,0 +1,198 @@ -+/* -+ * (C) Copyright 2018 -+ * NVIDIA Corporation -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "../p2571/max77620_init.h" -+#include "pinmux-config-p3450-0000.h" -+ -+void pin_mux_mmc(void) -+{ -+ struct udevice *dev; -+ uchar val; -+ int ret; -+ -+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ -+ debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); -+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); -+ if (ret) { -+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__); -+ return; -+ } -+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ -+ val = 0xF2; -+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); -+ if (ret) -+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); -+ -+ /* Disable LDO4 discharge */ -+ ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); -+ if (ret) { -+ printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); -+ } else { -+ val &= ~BIT(1); /* ADE */ -+ ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); -+ if (ret) -+ printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); -+ } -+ -+ /* Set MBLPD */ -+ ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); -+ if (ret) { -+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); -+ } else { -+ val |= BIT(6); /* MBLPD */ -+ ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); -+ if (ret) -+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); -+ } -+} -+ -+/* -+ * Routine: pinmux_init -+ * Description: Do individual peripheral pinmux configs -+ */ -+void pinmux_init(void) -+{ -+ pinmux_clear_tristate_input_clamping(); -+ -+ gpio_config_table(p3450_0000_gpio_inits, -+ ARRAY_SIZE(p3450_0000_gpio_inits)); -+ -+ pinmux_config_pingrp_table(p3450_0000_pingrps, -+ ARRAY_SIZE(p3450_0000_pingrps)); -+ -+ pinmux_config_drvgrp_table(p3450_0000_drvgrps, -+ ARRAY_SIZE(p3450_0000_drvgrps)); -+} -+ -+#ifdef CONFIG_PCI_TEGRA -+int tegra_pcie_board_init(void) -+{ -+ struct udevice *dev; -+ uchar val; -+ int ret; -+ -+ /* Turn on MAX77620 LDO1 to 1.05V for PEX power */ -+ debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__); -+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); -+ if (ret) { -+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__); -+ return -1; -+ } -+ /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ -+ val = 0xCA; -+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1); -+ if (ret) -+ printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret); -+ -+ return 0; -+} -+#endif /* PCI */ -+ -+static void ft_mac_address_setup(void *fdt) -+{ -+ const void *cboot_fdt = (const void *)cboot_boot_x0; -+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; -+ const char *path; -+ int offset, err; -+ -+ err = cboot_get_ethaddr(cboot_fdt, local_mac); -+ if (err < 0) -+ memset(local_mac, 0, ETH_ALEN); -+ -+ path = fdt_get_alias(fdt, "ethernet"); -+ if (!path) -+ return; -+ -+ debug("ethernet alias found: %s\n", path); -+ -+ offset = fdt_path_offset(fdt, path); -+ if (offset < 0) { -+ printf("ethernet alias points to absent node %s\n", path); -+ return; -+ } -+ -+ if (is_valid_ethaddr(local_mac)) { -+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, -+ ETH_ALEN); -+ if (!err) -+ debug("Local MAC address set: %pM\n", local_mac); -+ } -+ -+ if (eth_env_get_enetaddr("ethaddr", mac)) { -+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) { -+ err = fdt_setprop(fdt, offset, "mac-address", mac, -+ ETH_ALEN); -+ if (!err) -+ debug("MAC address set: %pM\n", mac); -+ } -+ } -+} -+ -+static int ft_copy_carveout(void *dst, const void *src, const char *node) -+{ -+ struct fdt_memory fb; -+ int err; -+ -+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); -+ if (err < 0) { -+ if (err != -FDT_ERR_NOTFOUND) -+ printf("failed to get carveout for %s: %d\n", node, -+ err); -+ -+ return err; -+ } -+ -+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", -+ &fb); -+ if (err < 0) { -+ printf("failed to set carveout for %s: %d\n", node, err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static void ft_carveout_setup(void *fdt) -+{ -+ const void *cboot_fdt = (const void *)cboot_boot_x0; -+ static const char * const nodes[] = { -+ "/host1x@50000000/dc@54200000", -+ "/host1x@50000000/dc@54240000", -+ }; -+ unsigned int i; -+ int err; -+ -+ for (i = 0; i < ARRAY_SIZE(nodes); i++) { -+ printf("copying carveout for %s...\n", nodes[i]); -+ -+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); -+ if (err < 0) { -+ if (err != -FDT_ERR_NOTFOUND) -+ printf("failed to copy carveout for %s: %d\n", -+ nodes[i], err); -+ -+ continue; -+ } -+ } -+} -+ -+int ft_board_setup(void *fdt, bd_t *bd) -+{ -+ ft_mac_address_setup(fdt); -+ ft_carveout_setup(fdt); -+ -+ return 0; -+} -diff --git a/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h b/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h -new file mode 100644 -index 0000000000..722da49735 ---- /dev/null -+++ b/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h -@@ -0,0 +1,265 @@ -+/* -+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+/* -+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! -+ * -+ * To generate this file, use the tegra-pinmux-scripts tool available from -+ * https://github.com/NVIDIA/tegra-pinmux-scripts -+ * Run "board-to-uboot.py p3450-0000". -+ */ -+ -+#ifndef _PINMUX_CONFIG_P3450_0000_H_ -+#define _PINMUX_CONFIG_P3450_0000_H_ -+ -+#define GPIO_INIT(_port, _gpio, _init) \ -+ { \ -+ .gpio = TEGRA_GPIO(_port, _gpio), \ -+ .init = TEGRA_GPIO_INIT_##_init, \ -+ } -+ -+static const struct tegra_gpio_config p3450_0000_gpio_inits[] = { -+ /* port, pin, init_val */ -+ GPIO_INIT(A, 5, IN), -+ GPIO_INIT(A, 6, OUT1), -+ GPIO_INIT(B, 4, IN), -+ GPIO_INIT(B, 5, IN), -+ GPIO_INIT(B, 6, IN), -+ GPIO_INIT(B, 7, IN), -+ GPIO_INIT(C, 0, IN), -+ GPIO_INIT(C, 1, IN), -+ GPIO_INIT(C, 2, IN), -+ GPIO_INIT(C, 3, IN), -+ GPIO_INIT(C, 4, IN), -+ GPIO_INIT(E, 6, IN), -+ GPIO_INIT(G, 2, IN), -+ GPIO_INIT(G, 3, IN), -+ GPIO_INIT(H, 0, OUT0), -+ GPIO_INIT(H, 2, IN), -+ GPIO_INIT(H, 3, OUT0), -+ GPIO_INIT(H, 4, OUT0), -+ GPIO_INIT(H, 5, IN), -+ GPIO_INIT(H, 6, IN), -+ GPIO_INIT(H, 7, OUT0), -+ GPIO_INIT(I, 0, OUT0), -+ GPIO_INIT(I, 1, IN), -+ GPIO_INIT(I, 2, OUT0), -+ GPIO_INIT(J, 4, IN), -+ GPIO_INIT(J, 5, IN), -+ GPIO_INIT(J, 6, IN), -+ GPIO_INIT(J, 7, IN), -+ GPIO_INIT(S, 5, IN), -+ GPIO_INIT(S, 7, OUT0), -+ GPIO_INIT(T, 0, OUT0), -+ GPIO_INIT(V, 0, IN), -+ GPIO_INIT(V, 1, IN), -+ GPIO_INIT(X, 3, OUT1), -+ GPIO_INIT(X, 4, IN), -+ GPIO_INIT(X, 5, IN), -+ GPIO_INIT(X, 6, IN), -+ GPIO_INIT(Y, 1, IN), -+ GPIO_INIT(Y, 2, IN), -+ GPIO_INIT(Z, 0, IN), -+ GPIO_INIT(Z, 2, IN), -+ GPIO_INIT(Z, 3, OUT0), -+ GPIO_INIT(BB, 0, IN), -+ GPIO_INIT(CC, 4, IN), -+ GPIO_INIT(DD, 0, IN), -+}; -+ -+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ -+ { \ -+ .pingrp = PMUX_PINGRP_##_pingrp, \ -+ .func = PMUX_FUNC_##_mux, \ -+ .pull = PMUX_PULL_##_pull, \ -+ .tristate = PMUX_TRI_##_tri, \ -+ .io = PMUX_PIN_##_io, \ -+ .od = PMUX_PIN_OD_##_od, \ -+ .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ -+ .lock = PMUX_PIN_LOCK_DEFAULT, \ -+ } -+ -+static const struct pmux_pingrp_config p3450_0000_pingrps[] = { -+ /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ -+ PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), -+ PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), -+ PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PA6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(SPI2_MOSI_PB4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI2_MISO_PB5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI2_SCK_PB6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI2_CS0_PB7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(UART3_RTS_PD3, UARTC, UP, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DMIC3_CLK_PE4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -+ PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -+ PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART2_RX_PG1, UARTB, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(UART2_RTS_PG2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(UART2_CTS_PG3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(NFC_INT_PI1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART4_CTS_PI7, UARTD, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(DAP4_FS_PJ4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DAP4_DIN_PJ5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DAP4_DOUT_PJ6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DAP4_SCLK_PJ7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(CAM_AF_EN_PS5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART1_RX_PU1, UARTA, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(UART1_RTS_PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(UART1_CTS_PU3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(LCD_BL_PWM_PV0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(TOUCH_RST_PV6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(ALS_PROX_INT_PX3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(BUTTON_VOL_DOWN_PX7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(LCD_TE_PY2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -+ PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -+ PINCFG(CLK_32K_OUT_PY5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PZ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(DVFS_CLK_PBB2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -+ PINCFG(HDMI_INT_DP_HPD_PCC1, DP, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -+ PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(USB_VBUS_EN0_PCC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL), -+ PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -+ PINCFG(DP_HPD0_PCC6, DP, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -+ PINCFG(SPI2_CS1_PDD0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(CPU_PWR_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -+ PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -+ PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -+}; -+ -+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ -+ { \ -+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \ -+ .slwf = _slwf, \ -+ .slwr = _slwr, \ -+ .drvup = _drvup, \ -+ .drvdn = _drvdn, \ -+ .lpmd = PMUX_LPMD_##_lpmd, \ -+ .schmt = PMUX_SCHMT_##_schmt, \ -+ .hsm = PMUX_HSM_##_hsm, \ -+ } -+ -+static const struct pmux_drvgrp_config p3450_0000_drvgrps[] = { -+}; -+ -+#endif /* PINMUX_CONFIG_P3450_0000_H */ -diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig -new file mode 100644 -index 0000000000..3a95028279 ---- /dev/null -+++ b/configs/p3450-0000_defconfig -@@ -0,0 +1,55 @@ -+CONFIG_ARM=y -+CONFIG_TEGRA=y -+CONFIG_SYS_TEXT_BASE=0x80080000 -+CONFIG_TEGRA210=y -+CONFIG_TARGET_P3450_0000=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_OF_BOARD_SETUP=y -+CONFIG_CONSOLE_MUX=y -+CONFIG_SYS_STDIO_DEREGISTER=y -+CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " -+# CONFIG_CMD_IMI is not set -+CONFIG_CMD_DFU=y -+# CONFIG_CMD_FLASH is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_SF=y -+CONFIG_CMD_SPI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_SETEXPR is not set -+# CONFIG_CMD_NFS is not set -+CONFIG_CMD_EXT4_WRITE=y -+CONFIG_OF_LIVE=y -+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" -+CONFIG_DFU_MMC=y -+CONFIG_DFU_RAM=y -+CONFIG_DFU_SF=y -+CONFIG_SYS_I2C_TEGRA=y -+CONFIG_SPI_FLASH=y -+CONFIG_SF_DEFAULT_MODE=0 -+CONFIG_SF_DEFAULT_SPEED=24000000 -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_RTL8169=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_DM_PCI_COMPAT=y -+CONFIG_PCI_TEGRA=y -+CONFIG_SYS_NS16550=y -+CONFIG_TEGRA114_SPI=y -+CONFIG_USB=y -+CONFIG_DM_USB=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_TEGRA=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" -+CONFIG_USB_GADGET_VENDOR_NUM=0x0955 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x701a -+CONFIG_CI_UDC=y -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+# CONFIG_ENV_IS_IN_MMC is not set -diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h -new file mode 100644 -index 0000000000..7fc21820a7 ---- /dev/null -+++ b/include/configs/p3450-0000.h -@@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * (C) Copyright 2018-2019 NVIDIA Corporation. All rights reserved. -+ */ -+ -+#ifndef _P3450_0000_H -+#define _P3450_0000_H -+ -+#include -+ -+#include "tegra210-common.h" -+ -+/* High-level configuration options */ -+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" -+ -+/* Board-specific serial config */ -+#define CONFIG_TEGRA_ENABLE_UARTA -+ -+/* Only MMC1/PXE/DHCP for now, add USB back in later when supported */ -+#define BOOT_TARGET_DEVICES(func) \ -+ func(MMC, mmc, 0) \ -+ func(PXE, pxe, na) \ -+ func(DHCP, dhcp, na) -+ -+/* SPI */ -+#define CONFIG_SPI_FLASH_SIZE (4 << 20) -+ -+#include "tegra-common-usb-gadget.h" -+#include "tegra-common-post.h" -+ -+/* Crystal is 38.4MHz. clk_m runs at half that rate */ -+#define COUNTER_FREQUENCY 19200000 -+ -+#define BOARD_EXTRA_ENV_SETTINGS \ -+ "fdtfile=tegra210-p3450-0000.dtb\0" -+ -+#endif /* _P3450_0000_H */ -diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h -index fae0e761fb..321f27633e 100644 ---- a/include/configs/tegra-common-post.h -+++ b/include/configs/tegra-common-post.h -@@ -70,10 +70,6 @@ - "stderr=serial" STDOUT_LCD STDOUT_VIDEO "\0" \ - "" - --#ifndef BOARD_EXTRA_ENV_SETTINGS --#define BOARD_EXTRA_ENV_SETTINGS --#endif -- - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - - #ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS diff --git a/0011-Kconfig-add-btrfs-to-distro-boot.patch b/0011-Kconfig-add-btrfs-to-distro-boot.patch deleted file mode 100644 index c246352..0000000 --- a/0011-Kconfig-add-btrfs-to-distro-boot.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 7a367c6bdc04cf194160dad3eb0af1af579690b9 Mon Sep 17 00:00:00 2001 -From: Matthias Brugger -Date: Fri, 17 Jan 2020 20:59:02 +0100 -Subject: [PATCH] Kconfig: add btrfs to distro boot - -Some distributions use btrfs as the default file system. -Enable btrfs support by default when using distro boot for all -architectures but riscv, as it breaks compilation due to size problems. - -Signed-off-by: Matthias Brugger ---- - Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Kconfig b/Kconfig -index 92fc4fc135..b61ebf22f6 100644 ---- a/Kconfig -+++ b/Kconfig -@@ -93,6 +93,7 @@ config DISTRO_DEFAULTS - select HUSH_PARSER - select SUPPORT_RAW_INITRD - select SYS_LONGHELP -+ imply CMD_BTRFS if !RISCV && !MIPS - imply CMD_MII if NET - imply USB_STORAGE - imply USE_BOOTCOMMAND diff --git a/0012-configs-Re-sync-with-CONFIG_DISTRO_.patch b/0012-configs-Re-sync-with-CONFIG_DISTRO_.patch deleted file mode 100644 index 1b340d9..0000000 --- a/0012-configs-Re-sync-with-CONFIG_DISTRO_.patch +++ /dev/null @@ -1,88 +0,0 @@ -From f48a27f33d462c594a297eb315be92b43277630d Mon Sep 17 00:00:00 2001 -From: Matthias Brugger -Date: Fri, 17 Jan 2020 20:59:03 +0100 -Subject: [PATCH] configs: Re-sync with CONFIG_DISTRO_DEFAULTS - -CONFIG_DISTRO_DEFAULTS now enables CMD_BTRFS by default, -we can delete the config option in the corresponding default -configs. Other boards won't build with btrfs enabled so disable -the support by default. - -Signed-off-by: Matthias Brugger ---- - configs/am335x_evm_defconfig | 2 ++ - configs/sandbox64_defconfig | 1 - - configs/sandbox_defconfig | 1 - - configs/socfpga_arria10_defconfig | 2 ++ - configs/turris_mox_defconfig | 1 - - configs/turris_omnia_defconfig | 1 - - 6 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig -index ccb11c9b2a..1894678eea 100644 ---- a/configs/am335x_evm_defconfig -+++ b/configs/am335x_evm_defconfig -@@ -61,3 +61,5 @@ CONFIG_DYNAMIC_CRC_TABLE=y - CONFIG_RSA=y - CONFIG_LZO=y - # CONFIG_OF_LIBFDT_OVERLAY is not set -+# CONFIG_CMD_BTRFS is not set -+# CONFIG_FS_BTRFS is not set -diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig -index cc536ff0ba..1d625a9a84 100644 ---- a/configs/sandbox64_defconfig -+++ b/configs/sandbox64_defconfig -@@ -63,7 +63,6 @@ CONFIG_CMD_REGULATOR=y - CONFIG_CMD_AES=y - CONFIG_CMD_TPM=y - CONFIG_CMD_TPM_TEST=y --CONFIG_CMD_BTRFS=y - CONFIG_CMD_CBFS=y - CONFIG_CMD_CRAMFS=y - CONFIG_CMD_EXT4_WRITE=y -diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig -index 64245f7cdc..95b4d06171 100644 ---- a/configs/sandbox_defconfig -+++ b/configs/sandbox_defconfig -@@ -71,7 +71,6 @@ CONFIG_CMD_REGULATOR=y - CONFIG_CMD_AES=y - CONFIG_CMD_TPM=y - CONFIG_CMD_TPM_TEST=y --CONFIG_CMD_BTRFS=y - CONFIG_CMD_CBFS=y - CONFIG_CMD_CRAMFS=y - CONFIG_CMD_EXT4_WRITE=y -diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig -index b4826548eb..fa7a5681ec 100644 ---- a/configs/socfpga_arria10_defconfig -+++ b/configs/socfpga_arria10_defconfig -@@ -50,3 +50,5 @@ CONFIG_TIMER=y - CONFIG_SPL_TIMER=y - CONFIG_DESIGNWARE_APB_TIMER=y - # CONFIG_SPL_WDT is not set -+# CONFIG_CMD_BTRFS is not set -+# CONFIG_FS_BTRFS is not set -diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig -index b88cc4b842..89a1c73957 100644 ---- a/configs/turris_mox_defconfig -+++ b/configs/turris_mox_defconfig -@@ -32,7 +32,6 @@ CONFIG_CMD_TFTPPUT=y - CONFIG_CMD_CACHE=y - CONFIG_CMD_TIME=y - CONFIG_CMD_MVEBU_BUBT=y --CONFIG_CMD_BTRFS=y - CONFIG_CMD_EXT4_WRITE=y - CONFIG_MAC_PARTITION=y - CONFIG_OF_BOARD_FIXUP=y -diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig -index b6cb9a5f9d..160f1de656 100644 ---- a/configs/turris_omnia_defconfig -+++ b/configs/turris_omnia_defconfig -@@ -49,7 +49,6 @@ CONFIG_CMD_CACHE=y - CONFIG_CMD_TIME=y - CONFIG_CMD_AES=y - CONFIG_CMD_HASH=y --CONFIG_CMD_BTRFS=y - # CONFIG_SPL_PARTITION_UUIDS is not set - CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" - CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/0013-net-Add-support-for-Broadcom-GENETv.patch b/0013-net-Add-support-for-Broadcom-GENETv.patch deleted file mode 100644 index 3f3272c..0000000 --- a/0013-net-Add-support-for-Broadcom-GENETv.patch +++ /dev/null @@ -1,788 +0,0 @@ -From 992265c84e54272f419b38d7e5ec95ec743fc688 Mon Sep 17 00:00:00 2001 -From: Amit Singh Tomar -Date: Mon, 27 Jan 2020 01:14:42 +0000 -Subject: [PATCH] net: Add support for Broadcom GENETv5 Ethernet controller - -The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs -and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. -There is no publicly available documentation, so this driver is based -on the Linux driver. Compared to that the queue management is -drastically simplified, also we only support version 5 of the IP and -RGMII connections between MAC and PHY, as used on the RPi4. - -Signed-off-by: Amit Singh Tomar -Reviewed-by: Andre Przywara -[Andre: heavy cleanup and a few fixes] -Signed-off-by: Andre Przywara ---- - drivers/net/Kconfig | 7 + - drivers/net/Makefile | 1 + - drivers/net/bcmgenet.c | 729 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 737 insertions(+) - create mode 100644 drivers/net/bcmgenet.c - -diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig -index 142a2c6953..999714dd39 100644 ---- a/drivers/net/Kconfig -+++ b/drivers/net/Kconfig -@@ -136,6 +136,13 @@ config BCM6368_ETH - help - This driver supports the BCM6368 Ethernet MAC. - -+config BCMGENET -+ bool "BCMGENET V5 support" -+ depends on DM_ETH -+ select PHYLIB -+ help -+ This driver supports the BCMGENET Ethernet MAC. -+ - config DWC_ETH_QOS - bool "Synopsys DWC Ethernet QOS device support" - depends on DM_ETH -diff --git a/drivers/net/Makefile b/drivers/net/Makefile -index 30991834ec..6e0a68834d 100644 ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o - obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o - obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o - obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o -+obj-$(CONFIG_BCMGENET) += bcmgenet.o - obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o - obj-$(CONFIG_DRIVER_AX88180) += ax88180.o - obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o -diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c -new file mode 100644 -index 0000000000..8f4848aec6 ---- /dev/null -+++ b/drivers/net/bcmgenet.c -@@ -0,0 +1,729 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Amit Singh Tomar -+ * -+ * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) -+ * This driver is based on the Linux driver: -+ * drivers/net/ethernet/broadcom/genet/bcmgenet.c -+ * which is: Copyright (c) 2014-2017 Broadcom -+ * -+ * The hardware supports multiple queues (16 priority queues and one -+ * default queue), both for RX and TX. There are 256 DMA descriptors (both -+ * for TX and RX), and they live in MMIO registers. The hardware allows -+ * assigning descriptor ranges to queues, but we choose the most simple setup: -+ * All 256 descriptors are assigned to the default queue (#16). -+ * Also the Linux driver supports multiple generations of the MAC, whereas -+ * we only support v5, as used in the Raspberry Pi 4. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Register definitions derived from Linux source */ -+#define SYS_REV_CTRL 0x00 -+ -+#define SYS_PORT_CTRL 0x04 -+#define PORT_MODE_EXT_GPHY 3 -+ -+#define GENET_SYS_OFF 0x0000 -+#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) -+#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) -+ -+#define GENET_EXT_OFF 0x0080 -+#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) -+#define RGMII_LINK BIT(4) -+#define OOB_DISABLE BIT(5) -+#define RGMII_MODE_EN BIT(6) -+#define ID_MODE_DIS BIT(16) -+ -+#define GENET_RBUF_OFF 0x0300 -+#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) -+#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) -+#define RBUF_ALIGN_2B BIT(1) -+ -+#define GENET_UMAC_OFF 0x0800 -+#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) -+#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) -+#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) -+#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) -+#define UMAC_CMD (GENET_UMAC_OFF + 0x008) -+#define MDIO_CMD (GENET_UMAC_OFF + 0x614) -+#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) -+#define MDIO_START_BUSY BIT(29) -+#define MDIO_READ_FAIL BIT(28) -+#define MDIO_RD (2 << 26) -+#define MDIO_WR BIT(26) -+#define MDIO_PMD_SHIFT 21 -+#define MDIO_PMD_MASK 0x1f -+#define MDIO_REG_SHIFT 16 -+#define MDIO_REG_MASK 0x1f -+ -+#define CMD_TX_EN BIT(0) -+#define CMD_RX_EN BIT(1) -+#define UMAC_SPEED_10 0 -+#define UMAC_SPEED_100 1 -+#define UMAC_SPEED_1000 2 -+#define UMAC_SPEED_2500 3 -+#define CMD_SPEED_SHIFT 2 -+#define CMD_SPEED_MASK 3 -+#define CMD_SW_RESET BIT(13) -+#define CMD_LCL_LOOP_EN BIT(15) -+#define CMD_TX_EN BIT(0) -+#define CMD_RX_EN BIT(1) -+ -+#define MIB_RESET_RX BIT(0) -+#define MIB_RESET_RUNT BIT(1) -+#define MIB_RESET_TX BIT(2) -+ -+/* total number of Buffer Descriptors, same for Rx/Tx */ -+#define TOTAL_DESCS 256 -+#define RX_DESCS TOTAL_DESCS -+#define TX_DESCS TOTAL_DESCS -+ -+#define DEFAULT_Q 0x10 -+ -+/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. -+ * 1536 is multiple of 256 bytes -+ */ -+#define ENET_BRCM_TAG_LEN 6 -+#define ENET_PAD 8 -+#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ -+ VLAN_HLEN + ENET_BRCM_TAG_LEN + \ -+ ETH_FCS_LEN + ENET_PAD) -+ -+/* Tx/Rx Dma Descriptor common bits */ -+#define DMA_EN BIT(0) -+#define DMA_RING_BUF_EN_SHIFT 0x01 -+#define DMA_RING_BUF_EN_MASK 0xffff -+#define DMA_BUFLENGTH_MASK 0x0fff -+#define DMA_BUFLENGTH_SHIFT 16 -+#define DMA_RING_SIZE_SHIFT 16 -+#define DMA_OWN 0x8000 -+#define DMA_EOP 0x4000 -+#define DMA_SOP 0x2000 -+#define DMA_WRAP 0x1000 -+#define DMA_MAX_BURST_LENGTH 0x8 -+/* Tx specific DMA descriptor bits */ -+#define DMA_TX_UNDERRUN 0x0200 -+#define DMA_TX_APPEND_CRC 0x0040 -+#define DMA_TX_OW_CRC 0x0020 -+#define DMA_TX_DO_CSUM 0x0010 -+#define DMA_TX_QTAG_SHIFT 7 -+ -+/* DMA rings size */ -+#define DMA_RING_SIZE 0x40 -+#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) -+ -+/* DMA descriptor */ -+#define DMA_DESC_LENGTH_STATUS 0x00 -+#define DMA_DESC_ADDRESS_LO 0x04 -+#define DMA_DESC_ADDRESS_HI 0x08 -+#define DMA_DESC_SIZE 12 -+ -+#define GENET_RX_OFF 0x2000 -+#define GENET_RDMA_REG_OFF \ -+ (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) -+#define GENET_TX_OFF 0x4000 -+#define GENET_TDMA_REG_OFF \ -+ (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) -+ -+#define DMA_FC_THRESH_HI (RX_DESCS >> 4) -+#define DMA_FC_THRESH_LO 5 -+#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ -+ DMA_FC_THRESH_HI) -+ -+#define DMA_XOFF_THRESHOLD_SHIFT 16 -+ -+#define TDMA_RING_REG_BASE \ -+ (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) -+#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) -+#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) -+#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) -+#define DMA_RING_BUF_SIZE 0x10 -+#define DMA_START_ADDR 0x14 -+#define DMA_END_ADDR 0x1c -+#define DMA_MBUF_DONE_THRESH 0x24 -+#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) -+#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) -+ -+#define RDMA_RING_REG_BASE \ -+ (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) -+#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) -+#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) -+#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) -+#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) -+#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) -+ -+#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) -+#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) -+#define DMA_RING_CFG 0x00 -+#define DMA_CTRL 0x04 -+#define DMA_SCB_BURST_SIZE 0x0c -+ -+#define RX_BUF_LENGTH 2048 -+#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) -+#define RX_BUF_OFFSET 2 -+ -+struct bcmgenet_eth_priv { -+ char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); -+ void *mac_reg; -+ void *tx_desc_base; -+ void *rx_desc_base; -+ int tx_index; -+ int rx_index; -+ int c_index; -+ int phyaddr; -+ u32 interface; -+ u32 speed; -+ struct phy_device *phydev; -+ struct mii_dev *bus; -+}; -+ -+static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) -+{ -+ u32 reg; -+ -+ reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); -+ reg |= BIT(1); -+ writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); -+ udelay(10); -+ -+ reg &= ~BIT(1); -+ writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); -+ udelay(10); -+ -+ writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); -+ udelay(10); -+ -+ writel(0, priv->mac_reg + UMAC_CMD); -+ -+ writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); -+ udelay(2); -+ writel(0, priv->mac_reg + UMAC_CMD); -+ -+ /* clear tx/rx counter */ -+ writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, -+ priv->mac_reg + UMAC_MIB_CTRL); -+ writel(0, priv->mac_reg + UMAC_MIB_CTRL); -+ -+ writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); -+ -+ /* init rx registers, enable ip header optimization */ -+ reg = readl(priv->mac_reg + RBUF_CTRL); -+ reg |= RBUF_ALIGN_2B; -+ writel(reg, (priv->mac_reg + RBUF_CTRL)); -+ -+ writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); -+} -+ -+static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) -+{ -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ struct eth_pdata *pdata = dev_get_platdata(dev); -+ uchar *addr = pdata->enetaddr; -+ u32 reg; -+ -+ reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; -+ writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); -+ -+ reg = addr[4] << 8 | addr[5]; -+ writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); -+ -+ return 0; -+} -+ -+static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) -+{ -+ clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); -+ clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); -+ -+ writel(1, priv->mac_reg + UMAC_TX_FLUSH); -+ udelay(10); -+ writel(0, priv->mac_reg + UMAC_TX_FLUSH); -+} -+ -+static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) -+{ -+ u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; -+ -+ writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); -+ -+ setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); -+} -+ -+static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) -+{ -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; -+ u32 len_stat = length << DMA_BUFLENGTH_SHIFT; -+ ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); -+ u32 prod_index, cons; -+ u32 tries = 100; -+ -+ prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); -+ -+ /* There is actually no reason for the rounding here, but the ARMv7 -+ * implementation of flush_dcache_range() checks for aligned -+ * boundaries of the flushed range. -+ * Adjust them here to pass that check and avoid misleading messages. -+ */ -+ flush_dcache_range(packet_aligned, -+ packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); -+ -+ len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; -+ len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; -+ -+ /* Set-up packet for transmission */ -+ writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); -+ writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); -+ writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); -+ -+ /* Increment index and start transmission */ -+ if (++priv->tx_index >= TX_DESCS) -+ priv->tx_index = 0; -+ -+ prod_index++; -+ -+ /* Start Transmisson */ -+ writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); -+ -+ do { -+ cons = readl(priv->mac_reg + TDMA_CONS_INDEX); -+ } while ((cons & 0xffff) < prod_index && --tries); -+ if (!tries) -+ return -ETIMEDOUT; -+ -+ return 0; -+} -+ -+/* Check whether all cache lines affected by an invalidate are within -+ * the buffer, to make sure we don't accidentally lose unrelated dirty -+ * data stored nearby. -+ * Alignment of the buffer start address will be checked in the implementation -+ * of invalidate_dcache_range(). -+ */ -+static void invalidate_dcache_check(unsigned long addr, size_t size, -+ size_t buffer_size) -+{ -+ size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); -+ -+ if (unlikely(inval_size > buffer_size)) -+ printf("WARNING: Cache invalidate area exceeds buffer size\n"); -+ -+ invalidate_dcache_range(addr, addr + inval_size); -+} -+ -+static int bcmgenet_gmac_eth_recv(struct udevice *dev, -+ int flags, uchar **packetp) -+{ -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; -+ u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); -+ u32 length, addr; -+ -+ if (prod_index == priv->c_index) -+ return -EAGAIN; -+ -+ length = readl(desc_base + DMA_DESC_LENGTH_STATUS); -+ length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; -+ addr = readl(desc_base + DMA_DESC_ADDRESS_LO); -+ -+ invalidate_dcache_check(addr, length, RX_BUF_LENGTH); -+ -+ /* To cater for the IP header alignment the hardware does. -+ * This would actually not be needed if we don't program -+ * RBUF_ALIGN_2B -+ */ -+ *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; -+ -+ return length - RX_BUF_OFFSET; -+} -+ -+static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, -+ int length) -+{ -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ -+ /* Tell the MAC we have consumed that last receive buffer. */ -+ priv->c_index = (priv->c_index + 1) & 0xFFFF; -+ writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); -+ -+ /* Forward our descriptor pointer, wrapping around if needed. */ -+ if (++priv->rx_index >= RX_DESCS) -+ priv->rx_index = 0; -+ -+ return 0; -+} -+ -+static void rx_descs_init(struct bcmgenet_eth_priv *priv) -+{ -+ char *rxbuffs = &priv->rxbuffer[0]; -+ u32 len_stat, i; -+ void *desc_base = priv->rx_desc_base; -+ -+ priv->c_index = 0; -+ -+ len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; -+ -+ for (i = 0; i < RX_DESCS; i++) { -+ writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), -+ desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); -+ writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), -+ desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); -+ writel(len_stat, -+ desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); -+ } -+} -+ -+static void rx_ring_init(struct bcmgenet_eth_priv *priv) -+{ -+ writel(DMA_MAX_BURST_LENGTH, -+ priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); -+ -+ writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); -+ writel(0x0, priv->mac_reg + RDMA_READ_PTR); -+ writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); -+ writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, -+ priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); -+ -+ writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); -+ writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); -+ writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, -+ priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); -+ writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); -+ writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); -+} -+ -+static void tx_ring_init(struct bcmgenet_eth_priv *priv) -+{ -+ writel(DMA_MAX_BURST_LENGTH, -+ priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); -+ -+ writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); -+ writel(0x0, priv->mac_reg + TDMA_READ_PTR); -+ writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); -+ writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, -+ priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); -+ writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); -+ writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); -+ writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); -+ writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); -+ writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, -+ priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); -+ -+ writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); -+} -+ -+static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) -+{ -+ struct phy_device *phy_dev = priv->phydev; -+ u32 speed; -+ -+ switch (phy_dev->speed) { -+ case SPEED_1000: -+ speed = UMAC_SPEED_1000; -+ break; -+ case SPEED_100: -+ speed = UMAC_SPEED_100; -+ break; -+ case SPEED_10: -+ speed = UMAC_SPEED_10; -+ break; -+ default: -+ printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); -+ return -EINVAL; -+ } -+ -+ clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, -+ RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); -+ -+ writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); -+ -+ return 0; -+} -+ -+static int bcmgenet_gmac_eth_start(struct udevice *dev) -+{ -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ int ret; -+ -+ priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; -+ priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; -+ priv->tx_index = 0x0; -+ priv->rx_index = 0x0; -+ -+ bcmgenet_umac_reset(priv); -+ -+ bcmgenet_gmac_write_hwaddr(dev); -+ -+ /* Disable RX/TX DMA and flush TX queues */ -+ bcmgenet_disable_dma(priv); -+ -+ rx_ring_init(priv); -+ rx_descs_init(priv); -+ -+ tx_ring_init(priv); -+ -+ /* Enable RX/TX DMA */ -+ bcmgenet_enable_dma(priv); -+ -+ /* read PHY properties over the wire from generic PHY set-up */ -+ ret = phy_startup(priv->phydev); -+ if (ret) { -+ printf("bcmgenet: PHY startup failed: %d\n", ret); -+ return ret; -+ } -+ -+ /* Update MAC registers based on PHY property */ -+ ret = bcmgenet_adjust_link(priv); -+ if (ret) { -+ printf("bcmgenet: adjust PHY link failed: %d\n", ret); -+ return ret; -+ } -+ -+ /* Enable Rx/Tx */ -+ setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); -+ -+ return 0; -+} -+ -+static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) -+{ -+ struct phy_device *phydev; -+ int ret; -+ -+ phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); -+ if (!phydev) -+ return -ENODEV; -+ -+ phydev->supported &= PHY_GBIT_FEATURES; -+ if (priv->speed) { -+ ret = phy_set_supported(priv->phydev, priv->speed); -+ if (ret) -+ return ret; -+ } -+ phydev->advertising = phydev->supported; -+ -+ phy_connect_dev(phydev, dev); -+ -+ priv->phydev = phydev; -+ phy_config(priv->phydev); -+ -+ return 0; -+} -+ -+static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) -+{ -+ setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); -+} -+ -+static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, -+ int reg, u16 value) -+{ -+ struct udevice *dev = bus->priv; -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ u32 val; -+ -+ /* Prepare the read operation */ -+ val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | -+ (reg << MDIO_REG_SHIFT) | (0xffff & value); -+ writel_relaxed(val, priv->mac_reg + MDIO_CMD); -+ -+ /* Start MDIO transaction */ -+ bcmgenet_mdio_start(priv); -+ -+ return wait_for_bit_32(priv->mac_reg + MDIO_CMD, -+ MDIO_START_BUSY, false, 20, true); -+} -+ -+static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) -+{ -+ struct udevice *dev = bus->priv; -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ u32 val; -+ int ret; -+ -+ /* Prepare the read operation */ -+ val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); -+ writel_relaxed(val, priv->mac_reg + MDIO_CMD); -+ -+ /* Start MDIO transaction */ -+ bcmgenet_mdio_start(priv); -+ -+ ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, -+ MDIO_START_BUSY, false, 20, true); -+ if (ret) -+ return ret; -+ -+ val = readl_relaxed(priv->mac_reg + MDIO_CMD); -+ -+ return val & 0xffff; -+} -+ -+static int bcmgenet_mdio_init(const char *name, struct udevice *priv) -+{ -+ struct mii_dev *bus = mdio_alloc(); -+ -+ if (!bus) { -+ debug("Failed to allocate MDIO bus\n"); -+ return -ENOMEM; -+ } -+ -+ bus->read = bcmgenet_mdio_read; -+ bus->write = bcmgenet_mdio_write; -+ snprintf(bus->name, sizeof(bus->name), name); -+ bus->priv = (void *)priv; -+ -+ return mdio_register(bus); -+} -+ -+/* We only support RGMII (as used on the RPi4). */ -+static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) -+{ -+ phy_interface_t phy_mode = priv->interface; -+ -+ switch (phy_mode) { -+ case PHY_INTERFACE_MODE_RGMII: -+ case PHY_INTERFACE_MODE_RGMII_RXID: -+ writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); -+ break; -+ default: -+ printf("unknown phy mode: %d\n", priv->interface); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int bcmgenet_eth_probe(struct udevice *dev) -+{ -+ struct eth_pdata *pdata = dev_get_platdata(dev); -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ ofnode mdio_node; -+ const char *name; -+ u32 reg; -+ int ret; -+ u8 major; -+ -+ priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); -+ priv->interface = pdata->phy_interface; -+ priv->speed = pdata->max_speed; -+ -+ /* Read GENET HW version */ -+ reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); -+ major = (reg >> 24) & 0x0f; -+ if (major != 6) { -+ if (major == 5) -+ major = 4; -+ else if (major == 0) -+ major = 1; -+ -+ printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); -+ return -ENODEV; -+ } -+ -+ ret = bcmgenet_interface_set(priv); -+ if (ret) -+ return ret; -+ -+ writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL); -+ udelay(10); -+ /* disable MAC while updating its registers */ -+ writel(0, priv->mac_reg + UMAC_CMD); -+ /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ -+ writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); -+ -+ mdio_node = dev_read_first_subnode(dev); -+ name = ofnode_get_name(mdio_node); -+ -+ ret = bcmgenet_mdio_init(name, dev); -+ if (ret) -+ return ret; -+ -+ priv->bus = miiphy_get_dev_by_name(name); -+ -+ return bcmgenet_phy_init(priv, dev); -+} -+ -+static void bcmgenet_gmac_eth_stop(struct udevice *dev) -+{ -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ -+ clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); -+ -+ bcmgenet_disable_dma(priv); -+} -+ -+static const struct eth_ops bcmgenet_gmac_eth_ops = { -+ .start = bcmgenet_gmac_eth_start, -+ .write_hwaddr = bcmgenet_gmac_write_hwaddr, -+ .send = bcmgenet_gmac_eth_send, -+ .recv = bcmgenet_gmac_eth_recv, -+ .free_pkt = bcmgenet_gmac_free_pkt, -+ .stop = bcmgenet_gmac_eth_stop, -+}; -+ -+static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) -+{ -+ struct eth_pdata *pdata = dev_get_platdata(dev); -+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); -+ struct ofnode_phandle_args phy_node; -+ const char *phy_mode; -+ int ret; -+ -+ pdata->iobase = dev_read_addr(dev); -+ -+ /* Get phy mode from DT */ -+ pdata->phy_interface = -1; -+ phy_mode = dev_read_string(dev, "phy-mode"); -+ if (phy_mode) -+ pdata->phy_interface = phy_get_interface_by_name(phy_mode); -+ if (pdata->phy_interface == -1) { -+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); -+ return -EINVAL; -+ } -+ -+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, -+ &phy_node); -+ if (!ret) { -+ ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); -+ ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); -+ } -+ -+ return 0; -+} -+ -+/* The BCM2711 implementation has a limited burst length compared to a generic -+ * GENETv5 version, but we go with that shorter value (8) in both cases, for -+ * the sake of simplicity. -+ */ -+static const struct udevice_id bcmgenet_eth_ids[] = { -+ {.compatible = "brcm,genet-v5"}, -+ {.compatible = "brcm,bcm2711-genet-v5"}, -+ {} -+}; -+ -+U_BOOT_DRIVER(eth_bcmgenet) = { -+ .name = "eth_bcmgenet", -+ .id = UCLASS_ETH, -+ .of_match = bcmgenet_eth_ids, -+ .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, -+ .probe = bcmgenet_eth_probe, -+ .ops = &bcmgenet_gmac_eth_ops, -+ .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), -+ .platdata_auto_alloc_size = sizeof(struct eth_pdata), -+ .flags = DM_FLAG_ALLOC_PRIV_DMA, -+}; diff --git a/0014-rpi4-Update-memory-map-to-accommoda.patch b/0014-rpi4-Update-memory-map-to-accommoda.patch deleted file mode 100644 index 310fcf1..0000000 --- a/0014-rpi4-Update-memory-map-to-accommoda.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 5b819a7dad673e92864647d798970787c7b8e872 Mon Sep 17 00:00:00 2001 -From: Amit Singh Tomar -Date: Mon, 27 Jan 2020 01:14:43 +0000 -Subject: [PATCH] rpi4: Update memory map to accommodate scb devices - -Some of the devices(for instance, pcie and gnet controller) sitting on -SCB bus falls behind/below the memory range that we currenty have. - -This patch updates the memory range to map those devices correctly. - -Signed-off-by: Amit Singh Tomar -Reviewed-by: Andre Przywara -Signed-off-by: Andre Przywara ---- - arch/arm/mach-bcm283x/init.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 3b5f45b431..9966d6c833 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -42,9 +42,9 @@ static struct mm_region bcm2711_mem_map[] = { - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { -- .virt = 0xfe000000UL, -- .phys = 0xfe000000UL, -- .size = 0x01800000UL, -+ .virt = 0xfc000000UL, -+ .phys = 0xfc000000UL, -+ .size = 0x03800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN diff --git a/0015-rpi4-Enable-GENET-Ethernet-controll.patch b/0015-rpi4-Enable-GENET-Ethernet-controll.patch deleted file mode 100644 index 3c9e24e..0000000 --- a/0015-rpi4-Enable-GENET-Ethernet-controll.patch +++ /dev/null @@ -1,58 +0,0 @@ -From e61c092813f356caa2f0cb1656cb9e0ccd265f46 Mon Sep 17 00:00:00 2001 -From: Amit Singh Tomar -Date: Mon, 27 Jan 2020 01:14:44 +0000 -Subject: [PATCH] rpi4: Enable GENET Ethernet controller - -The Raspberry Pi 4 SoC features an integrated Gigabit Ethernet -controller, connected as a platform device. - -Enable the new driver in the three applicable defconfigs, to allow -TFTP booting on the board. - -Signed-off-by: Amit Singh Tomar -[Andre: Add joined and 32-bit configs] -Signed-off-by: Andre Przywara ---- - configs/rpi_4_32b_defconfig | 2 ++ - configs/rpi_4_defconfig | 2 ++ - configs/rpi_arm64_defconfig | 1 + - 3 files changed, 5 insertions(+) - -diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig -index 00f80f71ad..e7ea88bd4b 100644 ---- a/configs/rpi_4_32b_defconfig -+++ b/configs/rpi_4_32b_defconfig -@@ -24,6 +24,8 @@ CONFIG_DM_KEYBOARD=y - CONFIG_DM_MMC=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y -+CONFIG_DM_ETH=y -+CONFIG_BCMGENET=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index 8cf1bb81ff..b0f9cf1c0e 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -24,6 +24,8 @@ CONFIG_DM_KEYBOARD=y - CONFIG_DM_MMC=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y -+CONFIG_DM_ETH=y -+CONFIG_BCMGENET=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 10fbe0db92..00b3096481 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -36,6 +36,7 @@ CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y - CONFIG_USB_ETHER_LAN78XX=y - CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_BCMGENET=y - CONFIG_DM_VIDEO=y - CONFIG_VIDEO_BPP32=y - CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/_multibuild b/_multibuild index 3c35ffb..b770d94 100644 --- a/_multibuild +++ b/_multibuild @@ -56,7 +56,6 @@ p2371-2180 p2771-0000-500 paz00 - p3450-0000 pcm051rev3 pine64plus pinebook diff --git a/u-boot.changes b/u-boot.changes index 720a1fe..c1aa427 100644 --- a/u-boot.changes +++ b/u-boot.changes @@ -1,18 +1,3 @@ -------------------------------------------------------------------- -Tue Jan 28 10:29:54 UTC 2020 - Matthias Brugger - -Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.01-next - Add support for Jetson Nano. - Enable btrfs by default. (jsc#SLE-10302) - Add network support for RPi4 (jsc#SLE-7276) -* Patches added: - 0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch - 0011-Kconfig-add-btrfs-to-distro-boot.patch - 0012-configs-Re-sync-with-CONFIG_DISTRO_.patch - 0013-net-Add-support-for-Broadcom-GENETv.patch - 0014-rpi4-Update-memory-map-to-accommoda.patch - 0015-rpi4-Enable-GENET-Ethernet-controll.patch - ------------------------------------------------------------------- Wed Jan 22 08:09:47 UTC 2020 - Guillaume GARDET diff --git a/u-boot.spec b/u-boot.spec index 8aefc30..14af6a1 100644 --- a/u-boot.spec +++ b/u-boot.spec @@ -132,7 +132,7 @@ %if "%target" == "dragonboard410c" || "%target" == "dragonboard820c" %define is_armv8 1 %endif -%if "%target" == "geekbox" || "%target" == "hikey" || "%target" == "khadas-vim" || "%target" == "khadas-vim2" || "%target" == "libretech-ac" || "%target" == "libretech-cc" || "%target" == "ls1012afrdmqspi" || "%target" == "mvebudb-88f3720" || "%target" == "mvebudbarmada8k" || "%target" == "mvebuespressobin-88f3720" || "%target" == "mvebumcbin-88f8040" || "%target" == "odroid-c2" || "%target" == "p2371-2180" || "%target" == "p2771-0000-500" || "%target" == "p3450-0000" || "%target" == "poplar" +%if "%target" == "geekbox" || "%target" == "hikey" || "%target" == "khadas-vim" || "%target" == "khadas-vim2" || "%target" == "libretech-ac" || "%target" == "libretech-cc" || "%target" == "ls1012afrdmqspi" || "%target" == "mvebudb-88f3720" || "%target" == "mvebudbarmada8k" || "%target" == "mvebuespressobin-88f3720" || "%target" == "mvebumcbin-88f8040" || "%target" == "odroid-c2" || "%target" == "p2371-2180" || "%target" == "p2771-0000-500" || "%target" == "poplar" %define is_armv8 1 %endif %if "%target" == "avnetultra96rev1" || "%target" == "xilinxzynqmpgeneric" || "%target" == "xilinxzynqmpzcu102rev10" @@ -210,12 +210,6 @@ Patch0006: 0006-tools-zynqmpbif-Add-support-for-loa.patch Patch0007: 0007-boo-1123170-Remove-ubifs-support-fr.patch Patch0008: 0008-zynqmp-generic-fix-compilation.patch Patch0009: 0009-boo-1144161-Remove-nand-mtd-spi-dfu.patch -Patch0010: 0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch -Patch0011: 0011-Kconfig-add-btrfs-to-distro-boot.patch -Patch0012: 0012-configs-Re-sync-with-CONFIG_DISTRO_.patch -Patch0013: 0013-net-Add-support-for-Broadcom-GENETv.patch -Patch0014: 0014-rpi4-Update-memory-map-to-accommoda.patch -Patch0015: 0015-rpi4-Enable-GENET-Ethernet-controll.patch # Patches: end BuildRequires: bc BuildRequires: bison diff --git a/update_git.sh b/update_git.sh index d47ade3..ca3197b 100644 --- a/update_git.sh +++ b/update_git.sh @@ -13,7 +13,7 @@ set -e GIT_TREE=git://github.com/openSUSE/u-boot.git GIT_LOCAL_TREE=~/git/u-boot-opensuse -GIT_BRANCH=tumbleweed-2020.01-next +GIT_BRANCH=tumbleweed-2020.01 GIT_UPSTREAM_TAG=v2020.01 GIT_DIR=/dev/shm/u-boot-factory-git-dir CMP_DIR=/dev/shm/u-boot-factory-cmp-dir