From 9a5ce738148019ec53d4d66bfd53a17128fb2ff1 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 14 Dec 2023 09:25:49 +0100 Subject: [PATCH] pci: pcie-brcmstb: Add bcm2712 PCIe controller support PCIe controller have minor register map difference compared to bcm2711 variant. Handle this using device specific register offset. Signed-off-by: Ivan T. Ivanov --- drivers/pci/pcie_brcmstb.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c index cd45f0bee9..d63e715b2e 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -90,7 +90,6 @@ #define PCIE_MEM_WIN0_LIMIT_HI(win) \ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) -#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 #define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 #define PCIE_MSI_INTR2_CLR 0x4508 @@ -131,6 +130,10 @@ #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define SSC_STATUS_PLL_LOCK_SHIFT 11 +struct pcie_cfg_data { + unsigned long hard_debug_offs; +}; + /** * struct brcm_pcie - the PCIe controller state * @base: Base address of memory mapped IO registers of the controller @@ -141,6 +144,7 @@ struct brcm_pcie { void __iomem *base; + struct pcie_cfg_data *cfg; int gen; bool ssc; }; @@ -458,7 +462,7 @@ static int brcm_pcie_probe(struct udevice *dev) /* Take the bridge out of reset */ clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); - clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, + clrbits_le32(base + pcie->cfg->hard_debug_offs, PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); /* Wait for SerDes to be stable */ @@ -599,7 +603,7 @@ static int brcm_pcie_remove(struct udevice *dev) setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK); /* Turn off SerDes */ - setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, + setbits_le32(base + pcie->cfg->hard_debug_offs, PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); /* Shutdown bridge */ @@ -620,6 +624,8 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) if (!pcie->base) return -EINVAL; + pcie->cfg = (struct pcie_cfg_data *)dev_get_driver_data(dev); + pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); @@ -636,8 +642,17 @@ static const struct dm_pci_ops brcm_pcie_ops = { .write_config = brcm_pcie_write_config, }; +static const struct pcie_cfg_data bcm2711_cfg = { + .hard_debug_offs = 0x4204 +}; + +static const struct pcie_cfg_data bcm2712_cfg = { + .hard_debug_offs = 0x4304 +}; + static const struct udevice_id brcm_pcie_ids[] = { - { .compatible = "brcm,bcm2711-pcie" }, + { .compatible = "brcm,bcm2711-pcie", .data = (ulong)&bcm2711_cfg }, + { .compatible = "brcm,bcm2712-pcie", .data = (ulong)&bcm2712_cfg }, { } };