forked from pool/u-boot
93cf7ee2fd
Automatic submission by obs-autosubmit OBS-URL: https://build.opensuse.org/request/show/414973 OBS-URL: https://build.opensuse.org/package/show/openSUSE:Factory/u-boot?expand=0&rev=77
40 lines
1.3 KiB
Diff
40 lines
1.3 KiB
Diff
From 607baf77917bf079758ec6d60abf283cc701638c Mon Sep 17 00:00:00 2001
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From: Tom Rini <trini@konsulko.com>
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Date: Thu, 14 Jul 2016 17:36:18 -0400
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Subject: [PATCH] Revert "armv8: Enable CPUECTLR.SMPEN for coherency"
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Upon further review this breaks most other platforms as we need to check
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what core we're running on before touching it at all.
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This reverts commit d73718f3236c520a92efa401084c658e6cc067f3.
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Signed-off-by: Tom Rini <trini@konsulko.com>
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(cherry picked from commit 3a592a1349ac3961b0f4f2db0a8d9f128225d897)
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Signed-off-by: Andreas Färber <afaerber@suse.de>
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---
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arch/arm/cpu/armv8/start.S | 8 --------
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1 file changed, 8 deletions(-)
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diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
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index dfce469..670e323 100644
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--- a/arch/arm/cpu/armv8/start.S
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+++ b/arch/arm/cpu/armv8/start.S
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@@ -81,14 +81,6 @@ reset:
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msr cpacr_el1, x0 /* Enable FP/SIMD */
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0:
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- /* Enalbe SMPEN bit for coherency.
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- * This register is not architectural but at the moment
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- * this bit should be set for A53/A57/A72.
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- */
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- mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
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- orr x0, x0, #0x40
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- msr S3_1_c15_c2_1, x0
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-
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/* Apply ARM core specific erratas */
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bl apply_core_errata
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