forked from pool/u-boot
Guillaume GARDET
529744c22f
OBS-URL: https://build.opensuse.org/request/show/802701 OBS-URL: https://build.opensuse.org/package/show/hardware:boot/u-boot?expand=0&rev=98
39 lines
1.6 KiB
Diff
39 lines
1.6 KiB
Diff
From 278f85de3e80c3240448bb133af65520294ec590 Mon Sep 17 00:00:00 2001
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From: Sylwester Nawrocki <s.nawrocki@samsung.com>
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Date: Mon, 4 May 2020 14:45:21 +0200
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Subject: [PATCH] pci: Add some PCI Express capability register offset
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definitions
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Add PCI Express capability definitions required by the Broadcom
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STB PCIe controller driver.
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Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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---
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include/pci.h | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/include/pci.h b/include/pci.h
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index 5bf91a43af..5307478b44 100644
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--- a/include/pci.h
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+++ b/include/pci.h
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@@ -479,11 +479,17 @@
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#define PCI_EXP_DEVCTL 8 /* Device Control */
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#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
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#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
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+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
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+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
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#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
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#define PCI_EXP_LNKSTA 18 /* Link Status */
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+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
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+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
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+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
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#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
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#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
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#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
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+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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/* Include the ID list */
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