99 lines
3.1 KiB
Diff
99 lines
3.1 KiB
Diff
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References: bnc#745367
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# HG changeset patch
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# User Jan Beulich <jbeulich@suse.com>
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# Date 1329135150 -3600
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# Node ID 6ae5506e49abbe07b3b84c56cda114f59beb7ebe
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# Parent e953d536d3c6e344cf310f63ead9feda87cc67b0
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x86/vMCE: MC{G,i}_CTL handling adjustments
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- g_mcg_cap was read to determine whether MCG_CTL exists before it got
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initialized
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- h_mci_ctrl[] and dom_vmce()->mci_ctl[] both got initialized via
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memset() with an inappropriate size (hence causing a [minor?]
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information leak)
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Acked-by: Keir Fraser <keir@xen.org>
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--- a/xen/arch/x86/cpu/mcheck/mce.c
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+++ b/xen/arch/x86/cpu/mcheck/mce.c
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@@ -29,7 +29,7 @@ invbool_param("mce", mce_disabled);
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bool_t __read_mostly mce_broadcast = 0;
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bool_t is_mc_panic;
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unsigned int __read_mostly nr_mce_banks;
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-int __read_mostly firstbank;
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+unsigned int __read_mostly firstbank;
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static void intpose_init(void);
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static void mcinfo_clear(struct mc_info *);
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@@ -646,7 +646,7 @@ int mce_available(struct cpuinfo_x86 *c)
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* Check if bank 0 is usable for MCE. It isn't for AMD K7,
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* and Intel P6 family before model 0x1a.
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*/
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-int mce_firstbank(struct cpuinfo_x86 *c)
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+unsigned int mce_firstbank(struct cpuinfo_x86 *c)
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{
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if (c->x86 == 6) {
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if (c->x86_vendor == X86_VENDOR_AMD)
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--- a/xen/arch/x86/cpu/mcheck/mce.h
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+++ b/xen/arch/x86/cpu/mcheck/mce.h
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@@ -52,13 +52,13 @@ int is_vmce_ready(struct mcinfo_bank *ba
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int unmmap_broken_page(struct domain *d, mfn_t mfn, unsigned long gfn);
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u64 mce_cap_init(void);
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-extern int firstbank;
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+extern unsigned int firstbank;
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int intel_mce_rdmsr(uint32_t msr, uint64_t *val);
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int intel_mce_wrmsr(uint32_t msr, uint64_t val);
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int mce_available(struct cpuinfo_x86 *c);
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-int mce_firstbank(struct cpuinfo_x86 *c);
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+unsigned int mce_firstbank(struct cpuinfo_x86 *c);
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/* Helper functions used for collecting error telemetry */
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struct mc_info *x86_mcinfo_getptr(void);
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void mc_panic(char *s);
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--- a/xen/arch/x86/cpu/mcheck/vmce.c
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+++ b/xen/arch/x86/cpu/mcheck/vmce.c
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@@ -39,7 +39,7 @@ int vmce_init_msr(struct domain *d)
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return -ENOMEM;
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}
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memset(dom_vmce(d)->mci_ctl, ~0,
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- sizeof(dom_vmce(d)->mci_ctl));
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+ nr_mce_banks * sizeof(*dom_vmce(d)->mci_ctl));
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dom_vmce(d)->mcg_status = 0x0;
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dom_vmce(d)->mcg_cap = g_mcg_cap;
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@@ -437,7 +437,7 @@ int vmce_domain_inject(
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int vmce_init(struct cpuinfo_x86 *c)
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{
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u64 value;
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- int i;
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+ unsigned int i;
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if ( !h_mci_ctrl )
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{
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@@ -448,17 +448,17 @@ int vmce_init(struct cpuinfo_x86 *c)
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return -ENOMEM;
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}
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/* Don't care banks before firstbank */
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- memset(h_mci_ctrl, 0xff, sizeof(h_mci_ctrl));
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+ memset(h_mci_ctrl, ~0,
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+ min(firstbank, nr_mce_banks) * sizeof(*h_mci_ctrl));
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for (i = firstbank; i < nr_mce_banks; i++)
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rdmsrl(MSR_IA32_MCx_CTL(i), h_mci_ctrl[i]);
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}
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- if (g_mcg_cap & MCG_CTL_P)
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- rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl);
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-
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rdmsrl(MSR_IA32_MCG_CAP, value);
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/* For Guest vMCE usage */
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g_mcg_cap = value & ~MCG_CMCI_P;
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+ if (value & MCG_CTL_P)
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+ rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl);
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return 0;
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}
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