9e9b5acb9c
5604f239-x86-PV-properly-populate-descriptor-tables.patch 561bbc8b-VT-d-don-t-suppress-invalidation-address-write-when-0.patch 561d2046-VT-d-use-proper-error-codes-in-iommu_enable_x2apic_IR.patch 561d20a0-x86-hide-MWAITX-from-PV-domains.patch 561e3283-x86-NUMA-fix-SRAT-table-processor-entry-handling.patch - bsc#951845 - VUL-0: CVE-2015-7972: xen: x86: populate-on-demand balloon size inaccuracy can crash guests (XSA-153) xsa153-libxl.patch - bsc#950703 - VUL-1: CVE-2015-7969: xen: leak of main per-domain vcpu pointer array (DoS) (XSA-149) xsa149.patch - bsc#950705 - VUL-1: CVE-2015-7969: xen: x86: leak of per-domain profiling-related vcpu pointer array (DoS) (XSA-151) xsa151.patch - bsc#950706 - VUL-0: CVE-2015-7971: xen: x86: some pmu and profiling hypercalls log without rate limiting (XSA-152) xsa152.patch - Dropped 55dc7937-x86-IO-APIC-don-t-create-pIRQ-mapping-from-masked-RTE.patch 5604f239-x86-PV-properly-populate-descriptor-tables.patch - bsc#932267 - VUL-1: CVE-2015-4037: qemu,kvm,xen: insecure temporary file use in /net/slirp.c CVE-2015-4037-qemuu-smb-config-dir-name.patch CVE-2015-4037-qemut-smb-config-dir-name.patch - bsc#877642 - VUL-0: CVE-2014-0222: qemu: qcow1: validate L2 table size to avoid integer overflows OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=382
56 lines
1.9 KiB
Diff
56 lines
1.9 KiB
Diff
# Commit 710942e57fb42ff8f344ca82f6b678f67e38ae63
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# Date 2015-10-12 15:58:35 +0200
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# Author Jan Beulich <jbeulich@suse.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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VT-d: don't suppress invalidation address write when it is zero
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GFN zero is a valid address, and hence may need invalidation done for
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it just like for any other GFN.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Acked-by: Yang Zhang <yang.z.zhang@intel.com>
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--- a/xen/drivers/passthrough/vtd/iommu.c
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+++ b/xen/drivers/passthrough/vtd/iommu.c
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@@ -414,7 +414,7 @@ static int flush_iotlb_reg(void *_iommu,
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{
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struct iommu *iommu = (struct iommu *) _iommu;
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int tlb_offset = ecap_iotlb_offset(iommu->ecap);
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- u64 val = 0, val_iva = 0;
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+ u64 val = 0;
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unsigned long flags;
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/*
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@@ -435,7 +435,6 @@ static int flush_iotlb_reg(void *_iommu,
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switch ( type )
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{
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case DMA_TLB_GLOBAL_FLUSH:
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- /* global flush doesn't need set IVA_REG */
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val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
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break;
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case DMA_TLB_DSI_FLUSH:
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@@ -443,8 +442,6 @@ static int flush_iotlb_reg(void *_iommu,
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break;
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case DMA_TLB_PSI_FLUSH:
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val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
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- /* Note: always flush non-leaf currently */
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- val_iva = size_order | addr;
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break;
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default:
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BUG();
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@@ -457,8 +454,11 @@ static int flush_iotlb_reg(void *_iommu,
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spin_lock_irqsave(&iommu->register_lock, flags);
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/* Note: Only uses first TLB reg currently */
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- if ( val_iva )
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- dmar_writeq(iommu->reg, tlb_offset, val_iva);
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+ if ( type == DMA_TLB_PSI_FLUSH )
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+ {
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+ /* Note: always flush non-leaf currently. */
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+ dmar_writeq(iommu->reg, tlb_offset, size_order | addr);
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+ }
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dmar_writeq(iommu->reg, tlb_offset + 8, val);
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/* Make sure hardware complete it */
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