diff --git a/u_sync-pci-ids-with-Mesa-22.0.0.patch b/u_sync-pci-ids-with-Mesa-22.0.0.patch new file mode 100644 index 0000000..778f605 --- /dev/null +++ b/u_sync-pci-ids-with-Mesa-22.0.0.patch @@ -0,0 +1,747 @@ +diff --git a/hw/xfree86/dri2/pci_ids/crocus_pci_ids.h b/hw/xfree86/dri2/pci_ids/crocus_pci_ids.h +new file mode 100644 +index 000000000..9c9b6cd17 +--- /dev/null ++++ b/hw/xfree86/dri2/pci_ids/crocus_pci_ids.h +@@ -0,0 +1,104 @@ ++CHIPSET(0x29A2, i965, "BW", "Intel(R) 965G") ++CHIPSET(0x2992, i965, "BW", "Intel(R) 965Q") ++CHIPSET(0x2982, i965, "BW", "Intel(R) 965G") ++CHIPSET(0x2972, i965, "BW", "Intel(R) 946GZ") ++CHIPSET(0x2A02, i965, "CL", "Intel(R) 965GM") ++CHIPSET(0x2A12, i965, "CL", "Intel(R) 965GME/GLE") ++ ++CHIPSET(0x2A42, g4x, "CTG", "Mobile Intel® GM45 Express Chipset") ++CHIPSET(0x2E02, g4x, "ELK", "Intel(R) Integrated Graphics Device") ++CHIPSET(0x2E12, g4x, "ELK", "Intel(R) Q45/Q43") ++CHIPSET(0x2E22, g4x, "ELK", "Intel(R) G45/G43") ++CHIPSET(0x2E32, g4x, "ELK", "Intel(R) G41") ++CHIPSET(0x2E42, g4x, "ELK", "Intel(R) B43") ++CHIPSET(0x2E92, g4x, "ELK", "Intel(R) B43") ++ ++CHIPSET(0x0042, ilk, "ILK", "Intel(R) HD Graphics") ++CHIPSET(0x0046, ilk, "ILK", "Intel(R) HD Graphics") ++ ++CHIPSET(0x0102, snb_gt1, "SNB GT1", "Intel(R) HD Graphics 2000") ++CHIPSET(0x0112, snb_gt2, "SNB GT2", "Intel(R) HD Graphics 3000") ++CHIPSET(0x0122, snb_gt2, "SNB GT2", "Intel(R) HD Graphics 3000") ++CHIPSET(0x0106, snb_gt1, "SNB GT1", "Intel(R) HD Graphics 2000") ++CHIPSET(0x0116, snb_gt2, "SNB GT2", "Intel(R) HD Graphics 3000") ++CHIPSET(0x0126, snb_gt2, "SNB GT2", "Intel(R) HD Graphics 3000") ++CHIPSET(0x010A, snb_gt1, "SNB GT1", "Intel(R) HD Graphics 2000") ++ ++CHIPSET(0x0152, ivb_gt1, "IVB GT1", "Intel(R) HD Graphics 2500") ++CHIPSET(0x0162, ivb_gt2, "IVB GT2", "Intel(R) HD Graphics 4000") ++CHIPSET(0x0156, ivb_gt1, "IVB GT1", "Intel(R) HD Graphics 2500") ++CHIPSET(0x0166, ivb_gt2, "IVB GT2", "Intel(R) HD Graphics 4000") ++CHIPSET(0x015a, ivb_gt1, "IVB GT1", "Intel(R) HD Graphics") ++CHIPSET(0x016a, ivb_gt2, "IVB GT2", "Intel(R) HD Graphics P4000") ++ ++CHIPSET(0x0402, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0412, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4600") ++CHIPSET(0x0422, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0406, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0416, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4600") ++CHIPSET(0x0426, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x040A, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x041A, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics P4600/P4700") ++CHIPSET(0x042A, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x040B, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x041B, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x042B, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x040E, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x041E, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4400") ++CHIPSET(0x042E, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0C02, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0C12, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0C22, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0C06, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0C16, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0C26, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0C0A, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0C1A, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0C2A, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0C0B, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0C1B, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0C2B, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0C0E, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0C1E, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0C2E, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0A02, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0A12, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0A22, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0A06, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0A16, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4400") ++CHIPSET(0x0A26, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics 5000") ++CHIPSET(0x0A0A, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0A1A, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0A2A, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0A0B, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0A1B, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0A2B, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0A0E, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0A1E, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4200") ++CHIPSET(0x0A2E, hsw_gt3, "HSW GT3", "Intel(R) Iris(R) Graphics 5100") ++CHIPSET(0x0D02, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0D12, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4600") ++CHIPSET(0x0D22, hsw_gt3, "HSW GT3", "Intel(R) Iris(R) Pro Graphics 5200") ++CHIPSET(0x0D06, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0D16, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0D26, hsw_gt3, "HSW GT3", "Intel(R) Iris(R) Pro Graphics P5200") ++CHIPSET(0x0D0A, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0D1A, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0D2A, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0D0B, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0D1B, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0D2B, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++CHIPSET(0x0D0E, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") ++CHIPSET(0x0D1E, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") ++CHIPSET(0x0D2E, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") ++ ++CHIPSET(0x0F31, byt, "BYT", "Intel(R) HD Graphics") ++CHIPSET(0x0F32, byt, "BYT", "Intel(R) HD Graphics") ++CHIPSET(0x0F33, byt, "BYT", "Intel(R) HD Graphics") ++CHIPSET(0x0157, byt, "BYT", "Intel(R) HD Graphics") ++CHIPSET(0x0155, byt, "BYT", "Intel(R) HD Graphics") ++ ++CHIPSET(0x22B0, chv, "CHV", "Intel(R) HD Graphics") ++CHIPSET(0x22B1, chv, "BSW", "Intel(R) HD Graphics XXX") /* Overridden in brw_get_renderer_string */ ++CHIPSET(0x22B2, chv, "CHV", "Intel(R) HD Graphics") ++CHIPSET(0x22B3, chv, "CHV", "Intel(R) HD Graphics") +diff --git a/hw/xfree86/dri2/pci_ids/i810_pci_ids.h b/hw/xfree86/dri2/pci_ids/i810_pci_ids.h +deleted file mode 100644 +index 7f681925d..000000000 +--- a/hw/xfree86/dri2/pci_ids/i810_pci_ids.h ++++ /dev/null +@@ -1,4 +0,0 @@ +-CHIPSET(0x7121, I810, i8xx) +-CHIPSET(0x7123, I810_DC100, i8xx) +-CHIPSET(0x7125, I810_E, i8xx) +-CHIPSET(0x1132, I815, i8xx) +diff --git a/hw/xfree86/dri2/pci_ids/i915_pci_ids.h b/hw/xfree86/dri2/pci_ids/i915_pci_ids.h +index 1c43c8ec7..4cd1faf74 100644 +--- a/hw/xfree86/dri2/pci_ids/i915_pci_ids.h ++++ b/hw/xfree86/dri2/pci_ids/i915_pci_ids.h +@@ -1,7 +1,3 @@ +-CHIPSET(0x3577, I830_M, "Intel(R) 830M") +-CHIPSET(0x2562, 845_G, "Intel(R) 845G") +-CHIPSET(0x3582, I855_GM, "Intel(R) 852GM/855GM") +-CHIPSET(0x2572, I865_G, "Intel(R) 865G") + CHIPSET(0x2582, I915_G, "Intel(R) 915G") + CHIPSET(0x258A, E7221_G, "Intel(R) E7221G (i915)") + CHIPSET(0x2592, I915_GM, "Intel(R) 915GM") +diff --git a/hw/xfree86/dri2/pci_ids/i965_pci_ids.h b/hw/xfree86/dri2/pci_ids/i965_pci_ids.h +deleted file mode 100644 +index c4072e2ee..000000000 +--- a/hw/xfree86/dri2/pci_ids/i965_pci_ids.h ++++ /dev/null +@@ -1,252 +0,0 @@ +-#ifndef IRIS +-CHIPSET(0x29A2, i965, "Intel(R) 965G") +-CHIPSET(0x2992, i965, "Intel(R) 965Q") +-CHIPSET(0x2982, i965, "Intel(R) 965G") +-CHIPSET(0x2972, i965, "Intel(R) 946GZ") +-CHIPSET(0x2A02, i965, "Intel(R) 965GM") +-CHIPSET(0x2A12, i965, "Intel(R) 965GME/GLE") +-CHIPSET(0x2A42, g4x, "Mobile Intel® GM45 Express Chipset") +-CHIPSET(0x2E02, g4x, "Intel(R) Integrated Graphics Device") +-CHIPSET(0x2E12, g4x, "Intel(R) Q45/Q43") +-CHIPSET(0x2E22, g4x, "Intel(R) G45/G43") +-CHIPSET(0x2E32, g4x, "Intel(R) G41") +-CHIPSET(0x2E42, g4x, "Intel(R) B43") +-CHIPSET(0x2E92, g4x, "Intel(R) B43") +-CHIPSET(0x0042, ilk, "Intel(R) Ironlake Desktop") +-CHIPSET(0x0046, ilk, "Intel(R) Ironlake Mobile") +-CHIPSET(0x0102, snb_gt1, "Intel(R) Sandybridge Desktop") +-CHIPSET(0x0112, snb_gt2, "Intel(R) Sandybridge Desktop") +-CHIPSET(0x0122, snb_gt2, "Intel(R) Sandybridge Desktop") +-CHIPSET(0x0106, snb_gt1, "Intel(R) Sandybridge Mobile") +-CHIPSET(0x0116, snb_gt2, "Intel(R) Sandybridge Mobile") +-CHIPSET(0x0126, snb_gt2, "Intel(R) Sandybridge Mobile") +-CHIPSET(0x010A, snb_gt1, "Intel(R) Sandybridge Server") +-CHIPSET(0x0152, ivb_gt1, "Intel(R) Ivybridge Desktop") +-CHIPSET(0x0162, ivb_gt2, "Intel(R) Ivybridge Desktop") +-CHIPSET(0x0156, ivb_gt1, "Intel(R) Ivybridge Mobile") +-CHIPSET(0x0166, ivb_gt2, "Intel(R) Ivybridge Mobile") +-CHIPSET(0x015a, ivb_gt1, "Intel(R) Ivybridge Server") +-CHIPSET(0x016a, ivb_gt2, "Intel(R) Ivybridge Server") +-CHIPSET(0x0402, hsw_gt1, "Intel(R) Haswell Desktop") +-CHIPSET(0x0412, hsw_gt2, "Intel(R) Haswell Desktop") +-CHIPSET(0x0422, hsw_gt3, "Intel(R) Haswell Desktop") +-CHIPSET(0x0406, hsw_gt1, "Intel(R) Haswell Mobile") +-CHIPSET(0x0416, hsw_gt2, "Intel(R) Haswell Mobile") +-CHIPSET(0x0426, hsw_gt3, "Intel(R) Haswell Mobile") +-CHIPSET(0x040A, hsw_gt1, "Intel(R) Haswell Server") +-CHIPSET(0x041A, hsw_gt2, "Intel(R) Haswell Server") +-CHIPSET(0x042A, hsw_gt3, "Intel(R) Haswell Server") +-CHIPSET(0x040B, hsw_gt1, "Intel(R) Haswell") +-CHIPSET(0x041B, hsw_gt2, "Intel(R) Haswell") +-CHIPSET(0x042B, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x040E, hsw_gt1, "Intel(R) Haswell") +-CHIPSET(0x041E, hsw_gt2, "Intel(R) Haswell") +-CHIPSET(0x042E, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x0C02, hsw_gt1, "Intel(R) Haswell Desktop") +-CHIPSET(0x0C12, hsw_gt2, "Intel(R) Haswell Desktop") +-CHIPSET(0x0C22, hsw_gt3, "Intel(R) Haswell Desktop") +-CHIPSET(0x0C06, hsw_gt1, "Intel(R) Haswell Mobile") +-CHIPSET(0x0C16, hsw_gt2, "Intel(R) Haswell Mobile") +-CHIPSET(0x0C26, hsw_gt3, "Intel(R) Haswell Mobile") +-CHIPSET(0x0C0A, hsw_gt1, "Intel(R) Haswell Server") +-CHIPSET(0x0C1A, hsw_gt2, "Intel(R) Haswell Server") +-CHIPSET(0x0C2A, hsw_gt3, "Intel(R) Haswell Server") +-CHIPSET(0x0C0B, hsw_gt1, "Intel(R) Haswell") +-CHIPSET(0x0C1B, hsw_gt2, "Intel(R) Haswell") +-CHIPSET(0x0C2B, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x0C0E, hsw_gt1, "Intel(R) Haswell") +-CHIPSET(0x0C1E, hsw_gt2, "Intel(R) Haswell") +-CHIPSET(0x0C2E, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x0A02, hsw_gt1, "Intel(R) Haswell Desktop") +-CHIPSET(0x0A12, hsw_gt2, "Intel(R) Haswell Desktop") +-CHIPSET(0x0A22, hsw_gt3, "Intel(R) Haswell Desktop") +-CHIPSET(0x0A06, hsw_gt1, "Intel(R) Haswell Mobile") +-CHIPSET(0x0A16, hsw_gt2, "Intel(R) Haswell Mobile") +-CHIPSET(0x0A26, hsw_gt3, "Intel(R) Haswell Mobile") +-CHIPSET(0x0A0A, hsw_gt1, "Intel(R) Haswell Server") +-CHIPSET(0x0A1A, hsw_gt2, "Intel(R) Haswell Server") +-CHIPSET(0x0A2A, hsw_gt3, "Intel(R) Haswell Server") +-CHIPSET(0x0A0B, hsw_gt1, "Intel(R) Haswell") +-CHIPSET(0x0A1B, hsw_gt2, "Intel(R) Haswell") +-CHIPSET(0x0A2B, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x0A0E, hsw_gt1, "Intel(R) Haswell") +-CHIPSET(0x0A1E, hsw_gt2, "Intel(R) Haswell") +-CHIPSET(0x0A2E, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x0D02, hsw_gt1, "Intel(R) Haswell Desktop") +-CHIPSET(0x0D12, hsw_gt2, "Intel(R) Haswell Desktop") +-CHIPSET(0x0D22, hsw_gt3, "Intel(R) Haswell Desktop") +-CHIPSET(0x0D06, hsw_gt1, "Intel(R) Haswell Mobile") +-CHIPSET(0x0D16, hsw_gt2, "Intel(R) Haswell Mobile") +-CHIPSET(0x0D26, hsw_gt3, "Intel(R) Haswell Mobile") +-CHIPSET(0x0D0A, hsw_gt1, "Intel(R) Haswell Server") +-CHIPSET(0x0D1A, hsw_gt2, "Intel(R) Haswell Server") +-CHIPSET(0x0D2A, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x0D0B, hsw_gt1, "Intel(R) Haswell") +-CHIPSET(0x0D1B, hsw_gt2, "Intel(R) Haswell") +-CHIPSET(0x0D2B, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x0D0E, hsw_gt1, "Intel(R) Haswell") +-CHIPSET(0x0D1E, hsw_gt2, "Intel(R) Haswell") +-CHIPSET(0x0D2E, hsw_gt3, "Intel(R) Haswell") +-CHIPSET(0x0F31, byt, "Intel(R) Bay Trail") +-CHIPSET(0x0F32, byt, "Intel(R) Bay Trail") +-CHIPSET(0x0F33, byt, "Intel(R) Bay Trail") +-CHIPSET(0x0157, byt, "Intel(R) Bay Trail") +-CHIPSET(0x0155, byt, "Intel(R) Bay Trail") +-CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherrytrail)") +-CHIPSET(0x22B1, chv, "Intel(R) HD Graphics XXX (Braswell)") /* Overridden in brw_get_renderer_string */ +-CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)") +-CHIPSET(0x22B3, chv, "Intel(R) HD Graphics (Cherryview)") +-#endif +-CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell GT1") +-CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell GT1") +-CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell GT1") +-CHIPSET(0x160B, bdw_gt1, "Intel(R) Broadwell GT1") +-CHIPSET(0x160D, bdw_gt1, "Intel(R) Broadwell GT1") +-CHIPSET(0x160E, bdw_gt1, "Intel(R) Broadwell GT1") +-CHIPSET(0x1612, bdw_gt2, "Intel(R) HD Graphics 5600 (Broadwell GT2)") +-CHIPSET(0x1616, bdw_gt2, "Intel(R) HD Graphics 5500 (Broadwell GT2)") +-CHIPSET(0x161A, bdw_gt2, "Intel(R) Broadwell GT2") +-CHIPSET(0x161B, bdw_gt2, "Intel(R) Broadwell GT2") +-CHIPSET(0x161D, bdw_gt2, "Intel(R) Broadwell GT2") +-CHIPSET(0x161E, bdw_gt2, "Intel(R) HD Graphics 5300 (Broadwell GT2)") +-CHIPSET(0x1622, bdw_gt3, "Intel(R) Iris Pro 6200 (Broadwell GT3e)") +-CHIPSET(0x1626, bdw_gt3, "Intel(R) HD Graphics 6000 (Broadwell GT3)") +-CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)") +-CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)") +-CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3") +-CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3") +-CHIPSET(0x1902, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)") +-CHIPSET(0x1906, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)") +-CHIPSET(0x190A, skl_gt1, "Intel(R) Skylake GT1") +-CHIPSET(0x190B, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)") +-CHIPSET(0x190E, skl_gt1, "Intel(R) Skylake GT1") +-CHIPSET(0x1912, skl_gt2, "Intel(R) HD Graphics 530 (Skylake GT2)") +-CHIPSET(0x1913, skl_gt2, "Intel(R) Skylake GT2f") +-CHIPSET(0x1915, skl_gt2, "Intel(R) Skylake GT2f") +-CHIPSET(0x1916, skl_gt2, "Intel(R) HD Graphics 520 (Skylake GT2)") +-CHIPSET(0x1917, skl_gt2, "Intel(R) Skylake GT2f") +-CHIPSET(0x191A, skl_gt2, "Intel(R) Skylake GT2") +-CHIPSET(0x191B, skl_gt2, "Intel(R) HD Graphics 530 (Skylake GT2)") +-CHIPSET(0x191D, skl_gt2, "Intel(R) HD Graphics P530 (Skylake GT2)") +-CHIPSET(0x191E, skl_gt2, "Intel(R) HD Graphics 515 (Skylake GT2)") +-CHIPSET(0x1921, skl_gt2, "Intel(R) HD Graphics 520 (Skylake GT2)") +-CHIPSET(0x1923, skl_gt3, "Intel(R) Skylake GT3e") +-CHIPSET(0x1926, skl_gt3, "Intel(R) Iris Graphics 540 (Skylake GT3e)") +-CHIPSET(0x1927, skl_gt3, "Intel(R) Iris Graphics 550 (Skylake GT3e)") +-CHIPSET(0x192A, skl_gt4, "Intel(R) Skylake GT4") +-CHIPSET(0x192B, skl_gt3, "Intel(R) Iris Graphics 555 (Skylake GT3e)") +-CHIPSET(0x192D, skl_gt3, "Intel(R) Iris Graphics P555 (Skylake GT3e)") +-CHIPSET(0x1932, skl_gt4, "Intel(R) Iris Pro Graphics 580 (Skylake GT4e)") +-CHIPSET(0x193A, skl_gt4, "Intel(R) Iris Pro Graphics P580 (Skylake GT4e)") +-CHIPSET(0x193B, skl_gt4, "Intel(R) Iris Pro Graphics 580 (Skylake GT4e)") +-CHIPSET(0x193D, skl_gt4, "Intel(R) Iris Pro Graphics P580 (Skylake GT4e)") +-CHIPSET(0x0A84, bxt, "Intel(R) HD Graphics (Broxton)") +-CHIPSET(0x1A84, bxt, "Intel(R) HD Graphics (Broxton)") +-CHIPSET(0x1A85, bxt_2x6, "Intel(R) HD Graphics (Broxton 2x6)") +-CHIPSET(0x5A84, bxt, "Intel(R) HD Graphics 505 (Broxton)") +-CHIPSET(0x5A85, bxt_2x6, "Intel(R) HD Graphics 500 (Broxton 2x6)") +-CHIPSET(0x5902, kbl_gt1, "Intel(R) HD Graphics 610 (Kaby Lake GT1)") +-CHIPSET(0x5906, kbl_gt1, "Intel(R) HD Graphics 610 (Kaby Lake GT1)") +-CHIPSET(0x590A, kbl_gt1, "Intel(R) Kabylake GT1") +-CHIPSET(0x5908, kbl_gt1, "Intel(R) Kabylake GT1") +-CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabylake GT1") +-CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1") +-CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5") +-CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5") +-CHIPSET(0x5917, kbl_gt2, "Intel(R) UHD Graphics 620 (Kabylake GT2)") +-CHIPSET(0x5912, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)") +-CHIPSET(0x5916, kbl_gt2, "Intel(R) HD Graphics 620 (Kaby Lake GT2)") +-CHIPSET(0x591A, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)") +-CHIPSET(0x591B, kbl_gt2, "Intel(R) HD Graphics 630 (Kaby Lake GT2)") +-CHIPSET(0x591D, kbl_gt2, "Intel(R) HD Graphics P630 (Kaby Lake GT2)") +-CHIPSET(0x591E, kbl_gt2, "Intel(R) HD Graphics 615 (Kaby Lake GT2)") +-CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F") +-CHIPSET(0x5923, kbl_gt3, "Intel(R) Kabylake GT3") +-CHIPSET(0x5926, kbl_gt3, "Intel(R) Iris Plus Graphics 640 (Kaby Lake GT3e)") +-CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3e)") +-CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4") +-CHIPSET(0x591C, kbl_gt2, "Intel(R) Amber Lake (Kabylake) GT2") +-CHIPSET(0x87C0, kbl_gt2, "Intel(R) Amber Lake (Kabylake) GT2") +-CHIPSET(0x87CA, cfl_gt2, "Intel(R) Amber Lake (Coffeelake) GT2") +-CHIPSET(0x3184, glk, "Intel(R) UHD Graphics 605 (Geminilake)") +-CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)") +-CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)") +-CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)") +-CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)") +-CHIPSET(0x3E9C, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)") +-CHIPSET(0x3E91, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)") +-CHIPSET(0x3E92, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)") +-CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)") +-CHIPSET(0x3E98, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)") +-CHIPSET(0x3E9A, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)") +-CHIPSET(0x3E9B, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)") +-CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)") +-CHIPSET(0x3EA9, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)") +-CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)") +-CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)") +-CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)") +-CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)") +-CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 2x6 GT1)") +-CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT1)") +-CHIPSET(0x3EA0, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)") +-CHIPSET(0x3EA3, cfl_gt2, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT2)") +-CHIPSET(0x3EA2, cfl_gt3, "Intel(R) HD Graphics (Whiskey Lake 3x8 GT3)") +-CHIPSET(0x9B21, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9BA0, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9BA2, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9BA4, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9BA5, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9BA8, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9BAA, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9BAB, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9BAC, cfl_gt1, "Intel(R) HD Graphics (Comet Lake 2x6 GT1)") +-CHIPSET(0x9B41, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x9BC0, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x9BC2, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x9BC4, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x9BC5, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x9BC8, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x9BCA, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x9BCB, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x9BCC, cfl_gt2, "Intel(R) HD Graphics (Comet Lake 3x8 GT2)") +-CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)") +-CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)") +-CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)") +-CHIPSET(0x5A42, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)") +-CHIPSET(0x5A44, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)") +-CHIPSET(0x5A59, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)") +-CHIPSET(0x5A5A, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)") +-CHIPSET(0x5A5C, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)") +-CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)") +-CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)") +-CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)") +-CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)") +-CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)") +-CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)") +-CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)") +-CHIPSET(0x8A53, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)") +-CHIPSET(0x8A54, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)") +-CHIPSET(0x8A56, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)") +-CHIPSET(0x8A57, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)") +-CHIPSET(0x8A58, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)") +-CHIPSET(0x8A59, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)") +-CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)") +-CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)") +-CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)") +-CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)") +-CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)") +-CHIPSET(0x4500, ehl_4x8, "Intel(R) HD Graphics (Elkhart Lake 4x8)") +-CHIPSET(0x4571, ehl_4x8, "Intel(R) HD Graphics (Elkhart Lake 4x8)") +-CHIPSET(0x4551, ehl_4x4, "Intel(R) HD Graphics (Elkhart Lake 4x4)") +-CHIPSET(0x4541, ehl_2x4, "Intel(R) HD Graphics (Elkhart Lake 2x4)") +-CHIPSET(0x9A40, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)") +-CHIPSET(0x9A49, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)") +-CHIPSET(0x9A59, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)") +-CHIPSET(0x9A60, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)") +-CHIPSET(0x9A68, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)") +-CHIPSET(0x9A70, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)") +-CHIPSET(0x9A78, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)") +-CHIPSET(0x9AC0, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)") +-CHIPSET(0x9AC9, tg1_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)") +-CHIPSET(0x9AD9, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)") +-CHIPSET(0x9AF8, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1X2X16 GT2)") +diff --git a/hw/xfree86/dri2/pci_ids/pci_id_driver_map.h b/hw/xfree86/dri2/pci_ids/pci_id_driver_map.h +index 04f372279..6077d2641 100644 +--- a/hw/xfree86/dri2/pci_ids/pci_id_driver_map.h ++++ b/hw/xfree86/dri2/pci_ids/pci_id_driver_map.h +@@ -8,31 +8,17 @@ + #endif + + static const int i915_chip_ids[] = { +-#define CHIPSET(chip, desc, name) chip, ++#define CHIPSET(chip, name, desc) chip, + #include "pci_ids/i915_pci_ids.h" + #undef CHIPSET + }; + +-static const int i965_chip_ids[] = { +-#define CHIPSET(chip, family, name) chip, +-#include "pci_ids/i965_pci_ids.h" ++static const int crocus_chip_ids[] = { ++#define CHIPSET(chip, family, name, desc) chip, ++#include "pci_ids/crocus_pci_ids.h" + #undef CHIPSET + }; + +-#ifndef DRIVER_MAP_GALLIUM_ONLY +-static const int r100_chip_ids[] = { +-#define CHIPSET(chip, name, family) chip, +-#include "pci_ids/radeon_pci_ids.h" +-#undef CHIPSET +-}; +- +-static const int r200_chip_ids[] = { +-#define CHIPSET(chip, name, family) chip, +-#include "pci_ids/r200_pci_ids.h" +-#undef CHIPSET +-}; +-#endif +- + static const int r300_chip_ids[] = { + #define CHIPSET(chip, name, family) chip, + #include "pci_ids/r300_pci_ids.h" +@@ -64,12 +50,8 @@ static const struct { + int num_chips_ids; + } driver_map[] = { + { 0x8086, "i915", i915_chip_ids, ARRAY_SIZE(i915_chip_ids) }, +- { 0x8086, "i965", i965_chip_ids, ARRAY_SIZE(i965_chip_ids) }, +- { 0x8086, "i965", NULL, -1 }, +-#ifndef DRIVER_MAP_GALLIUM_ONLY +- { 0x1002, "radeon", r100_chip_ids, ARRAY_SIZE(r100_chip_ids) }, +- { 0x1002, "r200", r200_chip_ids, ARRAY_SIZE(r200_chip_ids) }, +-#endif ++ { 0x8086, "crocus", crocus_chip_ids, ARRAY_SIZE(crocus_chip_ids) }, ++ { 0x8086, "iris", NULL, -1 }, + { 0x1002, "r300", r300_chip_ids, ARRAY_SIZE(r300_chip_ids) }, + { 0x1002, "r600", r600_chip_ids, ARRAY_SIZE(r600_chip_ids) }, + { 0x1002, "radeonsi", NULL, -1 }, +diff --git a/hw/xfree86/dri2/pci_ids/r200_pci_ids.h b/hw/xfree86/dri2/pci_ids/r200_pci_ids.h +deleted file mode 100644 +index f857ca704..000000000 +--- a/hw/xfree86/dri2/pci_ids/r200_pci_ids.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-CHIPSET(0x5148, R200_QH, R200) +-CHIPSET(0x514C, R200_QL, R200) +-CHIPSET(0x514D, R200_QM, R200) +-CHIPSET(0x4242, R200_BB, R200) +- +-CHIPSET(0x4966, RV250_If, RV250) +-CHIPSET(0x4967, RV250_Ig, RV250) +-CHIPSET(0x4C64, RV250_Ld, RV250) +-CHIPSET(0x4C66, RV250_Lf, RV250) +-CHIPSET(0x4C67, RV250_Lg, RV250) +- +-CHIPSET(0x4C6E, RV280_4C6E, RV280) +-CHIPSET(0x5960, RV280_5960, RV280) +-CHIPSET(0x5961, RV280_5961, RV280) +-CHIPSET(0x5962, RV280_5962, RV280) +-CHIPSET(0x5964, RV280_5964, RV280) +-CHIPSET(0x5965, RV280_5965, RV280) +-CHIPSET(0x5C61, RV280_5C61, RV280) +-CHIPSET(0x5C63, RV280_5C63, RV280) +- +-CHIPSET(0x5834, RS300_5834, RS300) +-CHIPSET(0x5835, RS300_5835, RS300) +-CHIPSET(0x7834, RS350_7834, RS300) +-CHIPSET(0x7835, RS350_7835, RS300) +diff --git a/hw/xfree86/dri2/pci_ids/radeon_pci_ids.h b/hw/xfree86/dri2/pci_ids/radeon_pci_ids.h +deleted file mode 100644 +index a9efc767d..000000000 +--- a/hw/xfree86/dri2/pci_ids/radeon_pci_ids.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-CHIPSET(0x4C57, RADEON_LW, RV200) +-CHIPSET(0x4C58, RADEON_LX, RV200) +-CHIPSET(0x4C59, RADEON_LY, RV100) +-CHIPSET(0x4C5A, RADEON_LZ, RV100) +-CHIPSET(0x5144, RADEON_QD, R100) +-CHIPSET(0x5145, RADEON_QE, R100) +-CHIPSET(0x5146, RADEON_QF, R100) +-CHIPSET(0x5147, RADEON_QG, R100) +-CHIPSET(0x5159, RADEON_QY, RV100) +-CHIPSET(0x515A, RADEON_QZ, RV100) +- +-CHIPSET(0x5157, RV200_QW, RV200) +-CHIPSET(0x5158, RV200_QX, RV200) +- +-CHIPSET(0x515E, RN50_515E, UNKNOWN) +-CHIPSET(0x5969, RN50_5969, UNKNOWN) +- +-CHIPSET(0x4136, RS100_4136, RS100) +-CHIPSET(0x4336, RS100_4336, RS100) +-CHIPSET(0x4137, RS200_4137, RS200) +-CHIPSET(0x4337, RS200_4337, RS200) +-CHIPSET(0x4237, RS250_4237, RS200) +-CHIPSET(0x4437, RS250_4437, RS200) +diff --git a/hw/xfree86/dri2/pci_ids/radeonsi_pci_ids.h b/hw/xfree86/dri2/pci_ids/radeonsi_pci_ids.h +deleted file mode 100644 +index 2ec8a1e24..000000000 +--- a/hw/xfree86/dri2/pci_ids/radeonsi_pci_ids.h ++++ /dev/null +@@ -1,237 +0,0 @@ +-CHIPSET(0x6780, TAHITI_6780, TAHITI) +-CHIPSET(0x6784, TAHITI_6784, TAHITI) +-CHIPSET(0x6788, TAHITI_6788, TAHITI) +-CHIPSET(0x678A, TAHITI_678A, TAHITI) +-CHIPSET(0x6790, TAHITI_6790, TAHITI) +-CHIPSET(0x6791, TAHITI_6791, TAHITI) +-CHIPSET(0x6792, TAHITI_6792, TAHITI) +-CHIPSET(0x6798, TAHITI_6798, TAHITI) +-CHIPSET(0x6799, TAHITI_6799, TAHITI) +-CHIPSET(0x679A, TAHITI_679A, TAHITI) +-CHIPSET(0x679B, TAHITI_679B, TAHITI) +-CHIPSET(0x679E, TAHITI_679E, TAHITI) +-CHIPSET(0x679F, TAHITI_679F, TAHITI) +- +-CHIPSET(0x6800, PITCAIRN_6800, PITCAIRN) +-CHIPSET(0x6801, PITCAIRN_6801, PITCAIRN) +-CHIPSET(0x6802, PITCAIRN_6802, PITCAIRN) +-CHIPSET(0x6806, PITCAIRN_6806, PITCAIRN) +-CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN) +-CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN) +-CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN) +-CHIPSET(0x6811, PITCAIRN_6811, PITCAIRN) +-CHIPSET(0x6816, PITCAIRN_6816, PITCAIRN) +-CHIPSET(0x6817, PITCAIRN_6817, PITCAIRN) +-CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN) +-CHIPSET(0x6819, PITCAIRN_6819, PITCAIRN) +-CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN) +- +-CHIPSET(0x6820, VERDE_6820, VERDE) +-CHIPSET(0x6821, VERDE_6821, VERDE) +-CHIPSET(0x6822, VERDE_6822, VERDE) +-CHIPSET(0x6823, VERDE_6823, VERDE) +-CHIPSET(0x6824, VERDE_6824, VERDE) +-CHIPSET(0x6825, VERDE_6825, VERDE) +-CHIPSET(0x6826, VERDE_6826, VERDE) +-CHIPSET(0x6827, VERDE_6827, VERDE) +-CHIPSET(0x6828, VERDE_6828, VERDE) +-CHIPSET(0x6829, VERDE_6829, VERDE) +-CHIPSET(0x682A, VERDE_682A, VERDE) +-CHIPSET(0x682B, VERDE_682B, VERDE) +-CHIPSET(0x682C, VERDE_682C, VERDE) +-CHIPSET(0x682D, VERDE_682D, VERDE) +-CHIPSET(0x682F, VERDE_682F, VERDE) +-CHIPSET(0x6830, VERDE_6830, VERDE) +-CHIPSET(0x6831, VERDE_6831, VERDE) +-CHIPSET(0x6835, VERDE_6835, VERDE) +-CHIPSET(0x6837, VERDE_6837, VERDE) +-CHIPSET(0x6838, VERDE_6838, VERDE) +-CHIPSET(0x6839, VERDE_6839, VERDE) +-CHIPSET(0x683B, VERDE_683B, VERDE) +-CHIPSET(0x683D, VERDE_683D, VERDE) +-CHIPSET(0x683F, VERDE_683F, VERDE) +- +-CHIPSET(0x6600, OLAND_6600, OLAND) +-CHIPSET(0x6601, OLAND_6601, OLAND) +-CHIPSET(0x6602, OLAND_6602, OLAND) +-CHIPSET(0x6603, OLAND_6603, OLAND) +-CHIPSET(0x6604, OLAND_6604, OLAND) +-CHIPSET(0x6605, OLAND_6605, OLAND) +-CHIPSET(0x6606, OLAND_6606, OLAND) +-CHIPSET(0x6607, OLAND_6607, OLAND) +-CHIPSET(0x6608, OLAND_6608, OLAND) +-CHIPSET(0x6610, OLAND_6610, OLAND) +-CHIPSET(0x6611, OLAND_6611, OLAND) +-CHIPSET(0x6613, OLAND_6613, OLAND) +-CHIPSET(0x6617, OLAND_6617, OLAND) +-CHIPSET(0x6620, OLAND_6620, OLAND) +-CHIPSET(0x6621, OLAND_6621, OLAND) +-CHIPSET(0x6623, OLAND_6623, OLAND) +-CHIPSET(0x6631, OLAND_6631, OLAND) +- +-CHIPSET(0x6660, HAINAN_6660, HAINAN) +-CHIPSET(0x6663, HAINAN_6663, HAINAN) +-CHIPSET(0x6664, HAINAN_6664, HAINAN) +-CHIPSET(0x6665, HAINAN_6665, HAINAN) +-CHIPSET(0x6667, HAINAN_6667, HAINAN) +-CHIPSET(0x666F, HAINAN_666F, HAINAN) +- +-CHIPSET(0x6640, BONAIRE_6640, BONAIRE) +-CHIPSET(0x6641, BONAIRE_6641, BONAIRE) +-CHIPSET(0x6646, BONAIRE_6646, BONAIRE) +-CHIPSET(0x6647, BONAIRE_6647, BONAIRE) +-CHIPSET(0x6649, BONAIRE_6649, BONAIRE) +-CHIPSET(0x6650, BONAIRE_6650, BONAIRE) +-CHIPSET(0x6651, BONAIRE_6651, BONAIRE) +-CHIPSET(0x6658, BONAIRE_6658, BONAIRE) +-CHIPSET(0x665C, BONAIRE_665C, BONAIRE) +-CHIPSET(0x665D, BONAIRE_665D, BONAIRE) +-CHIPSET(0x665F, BONAIRE_665F, BONAIRE) +- +-CHIPSET(0x9830, KABINI_9830, KABINI) +-CHIPSET(0x9831, KABINI_9831, KABINI) +-CHIPSET(0x9832, KABINI_9832, KABINI) +-CHIPSET(0x9833, KABINI_9833, KABINI) +-CHIPSET(0x9834, KABINI_9834, KABINI) +-CHIPSET(0x9835, KABINI_9835, KABINI) +-CHIPSET(0x9836, KABINI_9836, KABINI) +-CHIPSET(0x9837, KABINI_9837, KABINI) +-CHIPSET(0x9838, KABINI_9838, KABINI) +-CHIPSET(0x9839, KABINI_9839, KABINI) +-CHIPSET(0x983A, KABINI_983A, KABINI) +-CHIPSET(0x983B, KABINI_983B, KABINI) +-CHIPSET(0x983C, KABINI_983C, KABINI) +-CHIPSET(0x983D, KABINI_983D, KABINI) +-CHIPSET(0x983E, KABINI_983E, KABINI) +-CHIPSET(0x983F, KABINI_983F, KABINI) +- +-CHIPSET(0x9850, MULLINS_9850, MULLINS) +-CHIPSET(0x9851, MULLINS_9851, MULLINS) +-CHIPSET(0x9852, MULLINS_9852, MULLINS) +-CHIPSET(0x9853, MULLINS_9853, MULLINS) +-CHIPSET(0x9854, MULLINS_9854, MULLINS) +-CHIPSET(0x9855, MULLINS_9855, MULLINS) +-CHIPSET(0x9856, MULLINS_9856, MULLINS) +-CHIPSET(0x9857, MULLINS_9857, MULLINS) +-CHIPSET(0x9858, MULLINS_9858, MULLINS) +-CHIPSET(0x9859, MULLINS_9859, MULLINS) +-CHIPSET(0x985A, MULLINS_985A, MULLINS) +-CHIPSET(0x985B, MULLINS_985B, MULLINS) +-CHIPSET(0x985C, MULLINS_985C, MULLINS) +-CHIPSET(0x985D, MULLINS_985D, MULLINS) +-CHIPSET(0x985E, MULLINS_985E, MULLINS) +-CHIPSET(0x985F, MULLINS_985F, MULLINS) +- +-CHIPSET(0x1304, KAVERI_1304, KAVERI) +-CHIPSET(0x1305, KAVERI_1305, KAVERI) +-CHIPSET(0x1306, KAVERI_1306, KAVERI) +-CHIPSET(0x1307, KAVERI_1307, KAVERI) +-CHIPSET(0x1309, KAVERI_1309, KAVERI) +-CHIPSET(0x130A, KAVERI_130A, KAVERI) +-CHIPSET(0x130B, KAVERI_130B, KAVERI) +-CHIPSET(0x130C, KAVERI_130C, KAVERI) +-CHIPSET(0x130D, KAVERI_130D, KAVERI) +-CHIPSET(0x130E, KAVERI_130E, KAVERI) +-CHIPSET(0x130F, KAVERI_130F, KAVERI) +-CHIPSET(0x1310, KAVERI_1310, KAVERI) +-CHIPSET(0x1311, KAVERI_1311, KAVERI) +-CHIPSET(0x1312, KAVERI_1312, KAVERI) +-CHIPSET(0x1313, KAVERI_1313, KAVERI) +-CHIPSET(0x1315, KAVERI_1315, KAVERI) +-CHIPSET(0x1316, KAVERI_1316, KAVERI) +-CHIPSET(0x1317, KAVERI_1317, KAVERI) +-CHIPSET(0x1318, KAVERI_1318, KAVERI) +-CHIPSET(0x131B, KAVERI_131B, KAVERI) +-CHIPSET(0x131C, KAVERI_131C, KAVERI) +-CHIPSET(0x131D, KAVERI_131D, KAVERI) +- +-CHIPSET(0x67A0, HAWAII_67A0, HAWAII) +-CHIPSET(0x67A1, HAWAII_67A1, HAWAII) +-CHIPSET(0x67A2, HAWAII_67A2, HAWAII) +-CHIPSET(0x67A8, HAWAII_67A8, HAWAII) +-CHIPSET(0x67A9, HAWAII_67A9, HAWAII) +-CHIPSET(0x67AA, HAWAII_67AA, HAWAII) +-CHIPSET(0x67B0, HAWAII_67B0, HAWAII) +-CHIPSET(0x67B1, HAWAII_67B1, HAWAII) +-CHIPSET(0x67B8, HAWAII_67B8, HAWAII) +-CHIPSET(0x67B9, HAWAII_67B9, HAWAII) +-CHIPSET(0x67BA, HAWAII_67BA, HAWAII) +-CHIPSET(0x67BE, HAWAII_67BE, HAWAII) +- +-CHIPSET(0x6900, ICELAND_, ICELAND) +-CHIPSET(0x6901, ICELAND_, ICELAND) +-CHIPSET(0x6902, ICELAND_, ICELAND) +-CHIPSET(0x6903, ICELAND_, ICELAND) +-CHIPSET(0x6907, ICELAND_, ICELAND) +- +-CHIPSET(0x6920, TONGA_, TONGA) +-CHIPSET(0x6921, TONGA_, TONGA) +-CHIPSET(0x6928, TONGA_, TONGA) +-CHIPSET(0x6929, TONGA_, TONGA) +-CHIPSET(0x692B, TONGA_, TONGA) +-CHIPSET(0x692F, TONGA_, TONGA) +-CHIPSET(0x6930, TONGA_, TONGA) +-CHIPSET(0x6938, TONGA_, TONGA) +-CHIPSET(0x6939, TONGA_, TONGA) +- +-CHIPSET(0x9870, CARRIZO_, CARRIZO) +-CHIPSET(0x9874, CARRIZO_, CARRIZO) +-CHIPSET(0x9875, CARRIZO_, CARRIZO) +-CHIPSET(0x9876, CARRIZO_, CARRIZO) +-CHIPSET(0x9877, CARRIZO_, CARRIZO) +- +-CHIPSET(0x7300, FIJI_, FIJI) +- +-CHIPSET(0x67E0, POLARIS11_, POLARIS11) +-CHIPSET(0x67E1, POLARIS11_, POLARIS11) +-CHIPSET(0x67E3, POLARIS11_, POLARIS11) +-CHIPSET(0x67E7, POLARIS11_, POLARIS11) +-CHIPSET(0x67E8, POLARIS11_, POLARIS11) +-CHIPSET(0x67E9, POLARIS11_, POLARIS11) +-CHIPSET(0x67EB, POLARIS11_, POLARIS11) +-CHIPSET(0x67EF, POLARIS11_, POLARIS11) +-CHIPSET(0x67FF, POLARIS11_, POLARIS11) +- +-CHIPSET(0x67C0, POLARIS10_, POLARIS10) +-CHIPSET(0x67C1, POLARIS10_, POLARIS10) +-CHIPSET(0x67C2, POLARIS10_, POLARIS10) +-CHIPSET(0x67C4, POLARIS10_, POLARIS10) +-CHIPSET(0x67C7, POLARIS10_, POLARIS10) +-CHIPSET(0x67C8, POLARIS10_, POLARIS10) +-CHIPSET(0x67C9, POLARIS10_, POLARIS10) +-CHIPSET(0x67CA, POLARIS10_, POLARIS10) +-CHIPSET(0x67CC, POLARIS10_, POLARIS10) +-CHIPSET(0x67CF, POLARIS10_, POLARIS10) +-CHIPSET(0x67DF, POLARIS10_, POLARIS10) +- +-CHIPSET(0x98E4, STONEY_, STONEY) +- +-CHIPSET(0x6980, POLARIS12_, POLARIS12) +-CHIPSET(0x6981, POLARIS12_, POLARIS12) +-CHIPSET(0x6985, POLARIS12_, POLARIS12) +-CHIPSET(0x6986, POLARIS12_, POLARIS12) +-CHIPSET(0x6987, POLARIS12_, POLARIS12) +-CHIPSET(0x6995, POLARIS12_, POLARIS12) +-CHIPSET(0x6997, POLARIS12_, POLARIS12) +-CHIPSET(0x699F, POLARIS12_, POLARIS12) +- +-CHIPSET(0x694C, VEGAM_, VEGAM) +-CHIPSET(0x694E, VEGAM_, VEGAM) +- +-CHIPSET(0x6860, VEGA10_, VEGA10) +-CHIPSET(0x6861, VEGA10_, VEGA10) +-CHIPSET(0x6862, VEGA10_, VEGA10) +-CHIPSET(0x6863, VEGA10_, VEGA10) +-CHIPSET(0x6864, VEGA10_, VEGA10) +-CHIPSET(0x6867, VEGA10_, VEGA10) +-CHIPSET(0x6868, VEGA10_, VEGA10) +-CHIPSET(0x687F, VEGA10_, VEGA10) +-CHIPSET(0x686C, VEGA10_, VEGA10) +- +-CHIPSET(0x69A0, VEGA12_, VEGA12) +-CHIPSET(0x69A1, VEGA12_, VEGA12) +-CHIPSET(0x69A2, VEGA12_, VEGA12) +-CHIPSET(0x69A3, VEGA12_, VEGA12) +-CHIPSET(0x69AF, VEGA12_, VEGA12) +- +-CHIPSET(0x15DD, RAVEN_, RAVEN) diff --git a/xorg-x11-server.changes b/xorg-x11-server.changes index fec81bc..1be043e 100644 --- a/xorg-x11-server.changes +++ b/xorg-x11-server.changes @@ -1,3 +1,9 @@ +------------------------------------------------------------------- +Sun Mar 13 09:51:32 UTC 2022 - Stefan Dirsch + +- u_sync-pci-ids-with-Mesa-22.0.0.patch + * sync pci ids with Mesa 22.0.0 + ------------------------------------------------------------------- Tue Feb 22 18:24:20 UTC 2022 - Bjørn Lie diff --git a/xorg-x11-server.spec b/xorg-x11-server.spec index f7ec324..ffc52a9 100644 --- a/xorg-x11-server.spec +++ b/xorg-x11-server.spec @@ -246,6 +246,8 @@ Patch1940: U_xephyr-Don-t-check-for-SeatId-anymore.patch Patch1950: U_Fix-build-with-gcc-12.patch +Patch1960: u_sync-pci-ids-with-Mesa-22.0.0.patch + %description This package contains the X.Org Server. @@ -402,6 +404,7 @@ sh %{SOURCE92} --verify . %{SOURCE91} %patch1930 -p1 %patch1940 -p1 %patch1950 -p1 +%patch1960 -p1 %build %global _lto_cflags %{?_lto_cflags} -ffat-lto-objects