diff --git a/binutils-2.28-branch.diff b/binutils-2.28-branch.diff index f48f290..7be780a 100644 --- a/binutils-2.28-branch.diff +++ b/binutils-2.28-branch.diff @@ -155,12 +155,12 @@ index e7d4792..3381647 100644 ? h->dyn_relocs != NULL : ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC)) diff --git a/bfd/version.h b/bfd/version.h -index eda06e4..4d79b22 100644 +index eda06e4..db90564 100644 --- a/bfd/version.h +++ b/bfd/version.h @@ -1,4 +1,4 @@ -#define BFD_VERSION_DATE 20170302 -+#define BFD_VERSION_DATE 20170308 ++#define BFD_VERSION_DATE 20170331 #define BFD_VERSION @bfd_version@ #define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@ #define REPORT_BUGS_TO @report_bugs_to@ @@ -273,20 +273,225 @@ index baddf34..82119ef 100755 with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" diff --git a/gas/ChangeLog b/gas/ChangeLog -index 8a586ad..fa9ecbe 100644 +index 8a586ad..904e0b9 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog -@@ -2,6 +2,10 @@ - - * configure: Regenerate. - +@@ -1,3 +1,61 @@ ++2017-03-21 Palmer Dabbbelt ++ ++ * config/tc-riscv.c (md_show_usage): Remove defuct -m32, -m64, ++ -msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't ++ print an invalid default ISA string. ++ * doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options. ++ ++2017-03-14 Kito Cheng ++ ++ * config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate ++ encoding format, which can accept 0-valued immediates. ++ (riscv_ip): Likewise. ++ ++2017-03-02 Kuan-Lin Chen ++ ++ * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define. ++ ++2017-03-02 Kuan-Lin Chen ++ ++ * config/tc-riscv.c (md_apply_fix): Set fx_frag and ++ fx_next->fx_frag for CFA_advance_loc relocations. ++ ++2017-03-02 Kuan-Lin Chen ++ ++ * config/tc-riscv.c (md_apply_fix): Compute the correct offsets ++ for CFA relocations. ++ ++2017-03-27 Alan Modra ++ ++ PR 21303 ++ * testsuite/gas/ppc/pr21303.d, ++ * testsuite/gas/ppc/pr21303.s: New test ++ * testsuite/gas/ppc/ppc.exp: Run it. ++ ++2017-03-21 Andreas Krebbel ++ ++ Backport from mainline ++ 2017-03-21 Andreas Krebbel ++ ++ * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2 ++ from cpu_table. Remove vx2, and novx2 from cpu_flags. ++ ++2017-03-08 Peter Bergner ++ ++ * testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option. ++ (objdump): Use the -Mpower8 option. ++ ++2017-03-08 Peter Bergner ++ ++ Apply from master. ++ 2017-03-08 Peter Bergner ++ * testsuite/gas/ppc/power9.d New test. ++ * testsuite/gas/ppc/power9.s: Likewise. ++ +2017-03-02 Tristan Gingold + + * configure: Regenerate. + - 2017-02-28 Alan Modra + 2017-03-02 Tristan Gingold - * config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define. + * configure: Regenerate. +diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c +index ec5b0bb..649c3e8 100644 +--- a/gas/config/tc-riscv.c ++++ b/gas/config/tc-riscv.c +@@ -500,6 +500,7 @@ validate_riscv_insn (const struct riscv_opcode *opc) + case 'c': break; /* RS1, constrained to equal sp */ + case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; + case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; ++ case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; + case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; + case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; + case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; +@@ -1321,6 +1322,13 @@ rvc_imm_done: + ip->insn_opcode |= + ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); + goto rvc_imm_done; ++ case 'o': ++ if (my_getSmallExpression (imm_expr, imm_reloc, s, p) ++ || imm_expr->X_op != O_constant ++ || !VALID_RVC_IMM (imm_expr->X_add_number)) ++ break; ++ ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); ++ goto rvc_imm_done; + case 'K': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant +@@ -1837,6 +1845,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + unsigned int subtype; + bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); + bfd_boolean relaxable = FALSE; ++ offsetT loc; + + /* Remember value for tc_gen_reloc. */ + fixP->fx_addnumber = *valP; +@@ -1922,30 +1931,31 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + + case BFD_RELOC_RISCV_CFA: + /* Load the byte to get the subtype. */ +- subtype = bfd_get_8 (NULL, &fixP->fx_frag->fr_literal[fixP->fx_where]); ++ subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); ++ loc = fixP->fx_frag->fr_fix - (subtype & 7); + switch (subtype) + { + case DW_CFA_advance_loc1: +- fixP->fx_where++; +- fixP->fx_next->fx_where++; ++ fixP->fx_where = loc + 1; ++ fixP->fx_next->fx_where = loc + 1; + fixP->fx_r_type = BFD_RELOC_RISCV_SET8; + fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; + break; + + case DW_CFA_advance_loc2: + fixP->fx_size = 2; +- fixP->fx_where++; + fixP->fx_next->fx_size = 2; +- fixP->fx_next->fx_where++; ++ fixP->fx_where = loc + 1; ++ fixP->fx_next->fx_where = loc + 1; + fixP->fx_r_type = BFD_RELOC_RISCV_SET16; + fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; + break; + + case DW_CFA_advance_loc4: + fixP->fx_size = 4; +- fixP->fx_where++; + fixP->fx_next->fx_size = 4; +- fixP->fx_next->fx_where++; ++ fixP->fx_where = loc; ++ fixP->fx_next->fx_where = loc; + fixP->fx_r_type = BFD_RELOC_RISCV_SET32; + fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; + break; +@@ -1954,6 +1964,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) + if (subtype < 0x80 && (subtype & 0x40)) + { + /* DW_CFA_advance_loc */ ++ fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; ++ fixP->fx_next->fx_frag = fixP->fx_frag; + fixP->fx_r_type = BFD_RELOC_RISCV_SET6; + fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; + } +@@ -2069,7 +2081,6 @@ riscv_pre_output_hook (void) + { + if (frag->fr_type == rs_cfa) + { +- fragS *loc4_frag; + expressionS exp; + + symbolS *add_symbol = frag->fr_symbol->sy_value.X_add_symbol; +@@ -2080,8 +2091,7 @@ riscv_pre_output_hook (void) + exp.X_add_number = 0; + exp.X_op_symbol = op_symbol; + +- loc4_frag = (fragS *) frag->fr_opcode; +- fix_new_exp (loc4_frag, (int) frag->fr_offset, 1, &exp, 0, ++ fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, + BFD_RELOC_RISCV_CFA); + } + } +@@ -2455,15 +2465,10 @@ md_show_usage (FILE *stream) + { + fprintf (stream, _("\ + RISC-V options:\n\ +- -m32 assemble RV32 code\n\ +- -m64 assemble RV64 code (default)\n\ + -fpic generate position-independent code\n\ + -fno-pic don't generate position-independent code (default)\n\ +- -msoft-float don't use F registers for floating-point values\n\ +- -mhard-float use F registers for floating-point values (default)\n\ +- -mno-rvc disable the C extension for compressed instructions (default)\n\ +- -mrvc enable the C extension for compressed instructions\n\ +- -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\ ++ -march=ISA set the RISC-V architecture\n\ ++ -mabi=ABI set the RISC-V ABI\n\ + ")); + } + +diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h +index ae8d60e..e92b387 100644 +--- a/gas/config/tc-riscv.h ++++ b/gas/config/tc-riscv.h +@@ -112,4 +112,7 @@ extern int tc_riscv_regname_to_dw2regnum (char *); + #define elf_tc_final_processing riscv_elf_final_processing + extern void riscv_elf_final_processing (void); + ++/* Adjust debug_line after relaxation. */ ++#define DWARF2_USE_FIXED_ADVANCE_PC 1 ++ + #endif /* TC_RISCV */ +diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c +index 7c8087e..dccbe2c 100644 +--- a/gas/config/tc-s390.c ++++ b/gas/config/tc-s390.c +@@ -291,7 +291,7 @@ s390_parse_cpu (const char * arg, + { STRING_COMMA_LEN ("z13"), STRING_COMMA_LEN ("arch11"), + S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX }, + { STRING_COMMA_LEN ("arch12"), STRING_COMMA_LEN (""), +- S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX | S390_INSTR_FLAG_VX2 } ++ S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX } + }; + static struct + { +@@ -303,9 +303,7 @@ s390_parse_cpu (const char * arg, + { "htm", S390_INSTR_FLAG_HTM, TRUE }, + { "nohtm", S390_INSTR_FLAG_HTM, FALSE }, + { "vx", S390_INSTR_FLAG_VX, TRUE }, +- { "novx", S390_INSTR_FLAG_VX, FALSE }, +- { "vx2", S390_INSTR_FLAG_VX2, TRUE }, +- { "novx2", S390_INSTR_FLAG_VX2, FALSE } ++ { "novx", S390_INSTR_FLAG_VX, FALSE } + }; + unsigned int icpu; + char *ilp_bak; diff --git a/gas/configure b/gas/configure index ce7091e..e574cb8 100755 --- a/gas/configure @@ -373,6 +578,106 @@ index ce7091e..e574cb8 100755 configured by $0, generated by GNU Autoconf 2.64, with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" +diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi +index 0fa1b58..2efba4b 100644 +--- a/gas/doc/c-riscv.texi ++++ b/gas/doc/c-riscv.texi +@@ -26,6 +26,14 @@ The following table lists all availiable RISC-V specific options + @c man begin OPTIONS + @table @gcctabopt + ++@cindex @samp{-fpic} option, RISC-V ++@item -fpic ++Generate position-independent code ++ ++@cindex @samp{-fno-pic} option, RISC-V ++@item -fno-pic ++Don't generate position-independent code (default) ++ + @cindex @samp{-march=ISA} option, RISC-V + @item -march=ISA + Select the base isa, as specified by ISA. For example -march=rv32ima. +diff --git a/gas/testsuite/gas/ppc/altivec2.d b/gas/testsuite/gas/ppc/altivec2.d +index fc10fb5..26f9afa 100644 +--- a/gas/testsuite/gas/ppc/altivec2.d ++++ b/gas/testsuite/gas/ppc/altivec2.d +@@ -1,5 +1,5 @@ +-#as: -maltivec +-#objdump: -dr -Maltivec ++#as: -mpower8 ++#objdump: -dr -Mpower8 + #name: Altivec ISA 2.07 instructions + + .* +diff --git a/gas/testsuite/gas/ppc/power9.d b/gas/testsuite/gas/ppc/power9.d +index 9ba53d0..a67898f 100644 +--- a/gas/testsuite/gas/ppc/power9.d ++++ b/gas/testsuite/gas/ppc/power9.d +@@ -312,8 +312,9 @@ Disassembly of section \.text: + .*: (f1 31 9d 6f|6f 9d 31 f1) xscvdphp vs41,vs51 + .*: (f1 58 a7 6f|6f a7 58 f1) xvcvhpsp vs42,vs52 + .*: (f1 79 af 6f|6f af 79 f1) xvcvsphp vs43,vs53 +-.*: (4c 60 00 04|04 00 60 4c) addpcis r3,0 +-.*: (4c 60 00 04|04 00 60 4c) addpcis r3,0 ++.*: (4c 60 00 04|04 00 60 4c) lnia r3 ++.*: (4c 60 00 04|04 00 60 4c) lnia r3 ++.*: (4c 60 00 04|04 00 60 4c) lnia r3 + .*: (4c 80 00 05|05 00 80 4c) addpcis r4,1 + .*: (4c 80 00 05|05 00 80 4c) addpcis r4,1 + .*: (4c bf ff c4|c4 ff bf 4c) addpcis r5,-2 +diff --git a/gas/testsuite/gas/ppc/power9.s b/gas/testsuite/gas/ppc/power9.s +index 27f1122..4e3530f 100644 +--- a/gas/testsuite/gas/ppc/power9.s ++++ b/gas/testsuite/gas/ppc/power9.s +@@ -303,6 +303,7 @@ power9: + xscvdphp 41,51 + xvcvhpsp 42,52 + xvcvsphp 43,53 ++ lnia 3 + addpcis 3,0 + subpcis 3,0 + addpcis 4,1 +diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp +index 86db455..55367ad 100644 +--- a/gas/testsuite/gas/ppc/ppc.exp ++++ b/gas/testsuite/gas/ppc/ppc.exp +@@ -50,6 +50,7 @@ if { [istarget powerpc*-*-*] } then { + run_dump_test "common" + run_dump_test "476" + run_dump_test "a2" ++ run_dump_test "pr21303" + if { ![istarget powerpc*le-*-*] } then { + run_dump_test "vle" + run_dump_test "vle-reloc" +diff --git a/gas/testsuite/gas/ppc/pr21303.d b/gas/testsuite/gas/ppc/pr21303.d +new file mode 100644 +index 0000000..64761a4 +--- /dev/null ++++ b/gas/testsuite/gas/ppc/pr21303.d +@@ -0,0 +1,12 @@ ++#objdump: -d -Me200z4 ++#as: -a32 -mbig -me200z4 ++ ++.* ++ ++Disassembly of section \.text: ++ ++0+ <\.text>: ++ 0: 70 00 00 00 e_li r0,0 ++ 4: 7c 01 14 04 lbdcbx r0,r1,r2 ++ 8: 7c 01 14 44 lhdcbx r0,r1,r2 ++ c: 7c 01 14 84 lwdcbx r0,r1,r2 +diff --git a/gas/testsuite/gas/ppc/pr21303.s b/gas/testsuite/gas/ppc/pr21303.s +new file mode 100644 +index 0000000..890ba94 +--- /dev/null ++++ b/gas/testsuite/gas/ppc/pr21303.s +@@ -0,0 +1,5 @@ ++ .text ++ e_li 0, 0 ++ lbdcbx 0, 1, 2 ++ lhdcbx 0, 1, 2 ++ lwdcbx 0, 1, 2 diff --git a/gprof/ChangeLog b/gprof/ChangeLog index cc57e0d8..0c25d51 100644 --- a/gprof/ChangeLog @@ -474,6 +779,36 @@ index 43e0dac..9e6b8f3 100755 configured by $0, generated by GNU Autoconf 2.64, with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" +diff --git a/include/ChangeLog b/include/ChangeLog +index af39f33..9dd5f75 100644 +--- a/include/ChangeLog ++++ b/include/ChangeLog +@@ -1,3 +1,11 @@ ++2017-03-21 Andreas Krebbel ++ ++ Backport from mainline ++ 2017-03-21 Andreas Krebbel ++ ++ * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove. ++ (S390_INSTR_FLAG_FACILITY_MASK): Adjust value. ++ + 2017-02-28 Alan Modra + + * elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment. +diff --git a/include/opcode/s390.h b/include/opcode/s390.h +index 7ce5616..2e07664 100644 +--- a/include/opcode/s390.h ++++ b/include/opcode/s390.h +@@ -51,8 +51,7 @@ enum s390_opcode_cpu_val + + #define S390_INSTR_FLAG_HTM 0x2 + #define S390_INSTR_FLAG_VX 0x4 +-#define S390_INSTR_FLAG_VX2 0x8 +-#define S390_INSTR_FLAG_FACILITY_MASK 0xe ++#define S390_INSTR_FLAG_FACILITY_MASK 0x6 + + /* The opcode table is an array of struct s390_opcode. */ + diff --git a/ld/ChangeLog b/ld/ChangeLog index ba7d1d4..f4fda0c 100644 --- a/ld/ChangeLog @@ -592,10 +927,52 @@ index dafc348..54f160c 100644 exp_fold_tree_no_dot (s->assignment_statement.exp); break; diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog -index 7f01e54..3a19442 100644 +index 7f01e54..0517fd9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog -@@ -1,3 +1,19 @@ +@@ -1,3 +1,61 @@ ++2017-03-14 Kito Cheng ++ ++ * riscv-opc.c (riscv_opcodes> : Use the 'o' immediate encoding. ++ : Likewise. ++ Likewise. ++ ++2017-03-14 Kito Cheng ++ ++ * riscv-opc.c (riscv_opcodes) : Use match_opcode. ++ ++2017-03-13 Andrew Waterman ++ ++ * riscv-opc.c (riscv_opcodes) : Use match_opcode. ++ Likewise. ++ Likewise. ++ Likewise. ++ ++2017-03-27 Alan Modra ++ ++ PR 21303 ++ * ppc-dis.c (struct ppc_mopt): Comment. ++ (ppc_opts ): Move PPC_OPCODE_VLE from .sticky to .cpu. ++ ++2017-03-21 Andreas Krebbel ++ ++ Backport from mainline ++ 2017-03-21 Andreas Krebbel ++ ++ * s390-mkopc.c (main): Remove vx2 check. ++ * s390-opc.txt: Remove vx2 instruction flags. ++ ++2017-03-08 Peter Bergner ++ ++ * ppc-dis.c (ppc_opts) : Do not use PPC_OPCODE_ALTIVEC2; ++ : Do not use PPC_OPCODE_VSX3; ++ ++2017-03-08 Peter Bergner ++ ++ Apply from master. ++ 2017-03-08 Peter Bergner ++ * ppc-opc.c (powerpc_opcodes) : New extended mnemonic. ++ +2017-03-07 Alan Modra + + Apply from master @@ -701,8 +1078,61 @@ index be87eb2..0b352a4 100755 configured by $0, generated by GNU Autoconf 2.64, with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" +diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c +index e0eff7a..baa7388 100644 +--- a/opcodes/ppc-dis.c ++++ b/opcodes/ppc-dis.c +@@ -45,8 +45,19 @@ struct dis_private + (((struct dis_private *) ((INFO)->private_data))->dialect) + + struct ppc_mopt { ++ /* Option string, without -m or -M prefix. */ + const char *opt; ++ /* CPU option flags. */ + ppc_cpu_t cpu; ++ /* Flags that should stay on, even when combined with another cpu ++ option. This should only be used for generic options like ++ "-many" or "-maltivec" where it is reasonable to add some ++ capability to another cpu selection. The added flags are sticky ++ so that, for example, "-many -me500" and "-me500 -many" result in ++ the same assembler or disassembler behaviour. Do not use ++ "sticky" for specific cpus, as this will prevent that cpu's flags ++ from overriding the defaults set in powerpc_init_dialect or a ++ prior -m option. */ + ppc_cpu_t sticky; + }; + +@@ -93,7 +104,7 @@ struct ppc_mopt ppc_opts[] = { + | PPC_OPCODE_A2), + 0 }, + { "altivec", PPC_OPCODE_PPC, +- PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, ++ PPC_OPCODE_ALTIVEC }, + { "any", 0, + PPC_OPCODE_ANY }, + { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE, +@@ -108,8 +119,8 @@ struct ppc_mopt ppc_opts[] = { + { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE + | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI +- | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4), +- PPC_OPCODE_VLE }, ++ | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4), ++ 0 }, + { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300, + 0 }, + { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE +@@ -221,7 +232,7 @@ struct ppc_mopt ppc_opts[] = { + | PPC_OPCODE_E500), + PPC_OPCODE_VLE }, + { "vsx", PPC_OPCODE_PPC, +- PPC_OPCODE_VSX | PPC_OPCODE_VSX3 }, ++ PPC_OPCODE_VSX }, + { "htm", PPC_OPCODE_PPC, + PPC_OPCODE_HTM }, + }; diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c -index 9ac779c..30fd789 100644 +index 9ac779c..f7d1dcd 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -54,6 +54,7 @@ static long extract_bo (unsigned long, ppc_cpu_t, int *); @@ -953,7 +1383,24 @@ index 9ac779c..30fd789 100644 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ static unsigned long insert_sci8 (unsigned long insn, -@@ -4974,7 +5083,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -2443,6 +2552,8 @@ extract_vleil (unsigned long insn, + /* An DX form instruction. */ + #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) + #define DX_MASK DX (0x3f, 0x1f) ++/* An DX form instruction with the D bits specified. */ ++#define NODX_MASK (DX_MASK | 0x1fffc1) + + /* An EVSEL form instruction. */ + #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) +@@ -4155,6 +4266,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, + ++{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}}, + {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, + {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, + +@@ -4974,7 +5086,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, @@ -962,7 +1409,7 @@ index 9ac779c..30fd789 100644 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}}, {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, -@@ -5105,7 +5214,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -5105,7 +5217,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, @@ -971,7 +1418,7 @@ index 9ac779c..30fd789 100644 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, -@@ -6052,7 +6161,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6052,7 +6164,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, @@ -980,7 +1427,7 @@ index 9ac779c..30fd789 100644 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, -@@ -6167,7 +6276,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6167,7 +6279,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, @@ -989,7 +1436,7 @@ index 9ac779c..30fd789 100644 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, -@@ -6345,13 +6454,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6345,13 +6457,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, @@ -1005,7 +1452,7 @@ index 9ac779c..30fd789 100644 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, -@@ -6676,21 +6785,21 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6676,21 +6788,21 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, @@ -1033,7 +1480,7 @@ index 9ac779c..30fd789 100644 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, -@@ -6772,11 +6881,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6772,11 +6884,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, @@ -1049,7 +1496,7 @@ index 9ac779c..30fd789 100644 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, -@@ -6791,11 +6900,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6791,11 +6903,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, @@ -1065,7 +1512,7 @@ index 9ac779c..30fd789 100644 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}}, {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}}, -@@ -6803,11 +6912,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6803,11 +6915,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, @@ -1081,7 +1528,7 @@ index 9ac779c..30fd789 100644 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, -@@ -6839,11 +6948,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6839,11 +6951,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, @@ -1097,7 +1544,7 @@ index 9ac779c..30fd789 100644 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, -@@ -6851,8 +6960,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6851,8 +6963,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, @@ -1108,7 +1555,7 @@ index 9ac779c..30fd789 100644 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, -@@ -6881,14 +6990,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6881,14 +6993,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, @@ -1127,7 +1574,7 @@ index 9ac779c..30fd789 100644 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, -@@ -6917,11 +7026,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6917,11 +7029,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, @@ -1143,7 +1590,7 @@ index 9ac779c..30fd789 100644 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, -@@ -6941,8 +7050,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6941,8 +7053,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, @@ -1154,7 +1601,7 @@ index 9ac779c..30fd789 100644 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, -@@ -6961,8 +7070,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -6961,8 +7073,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, @@ -1165,3 +1612,387 @@ index 9ac779c..30fd789 100644 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index 867a026..2b18a1e 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -210,14 +210,14 @@ const struct riscv_opcode riscv_opcodes[] = + {"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, + {"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, + {"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, +-{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, ++{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS }, + {"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, +-{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, ++{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS }, + {"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, + {"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, +-{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, ++{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS }, + {"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, +-{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, ++{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS }, + {"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, + {"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, + {"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, +@@ -562,10 +562,10 @@ const struct riscv_opcode riscv_opcodes[] = + {"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 }, + {"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, + {"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, +-{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, ++{"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, + {"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, + {"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, +-{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 }, ++{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, + {"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 }, + {"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, + {"c.and", "C", "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, +@@ -574,8 +574,8 @@ const struct riscv_opcode riscv_opcodes[] = + {"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 }, + {"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 }, + {"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 }, +-{"c.andi", "C", "Cs,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, +-{"c.addiw", "64C", "d,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, ++{"c.andi", "C", "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, ++{"c.addiw", "64C", "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, + {"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, + {"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, + {"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 }, +diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c +index 8e0b332..68c55a9 100644 +--- a/opcodes/s390-mkopc.c ++++ b/opcodes/s390-mkopc.c +@@ -419,10 +419,6 @@ main (void) + && (str[2] == 0 || str[2] == ',')) { + flag_bits |= S390_INSTR_FLAG_VX; + str += 2; +- } else if (strncmp (str, "vx2", 3) == 0 +- && (str[3] == 0 || str[3] == ',')) { +- flag_bits |= S390_INSTR_FLAG_VX2; +- str += 3; + } else { + fprintf (stderr, "Couldn't parse flags string %s\n", + flags_string); +diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt +index b381587..51a17f3 100644 +--- a/opcodes/s390-opc.txt ++++ b/opcodes/s390-opc.txt +@@ -1685,146 +1685,146 @@ b93c ppno RRE_RR "perform pseudorandom number operation" z13 zarch + # Vector Enhancements Facility 1 + + e70000000085 vbperm VRR_VVV "vector bit permute" arch12 zarch +-e70000006004 vllezlf VRX_VRRD "vector load logical word element and zero - left aligned" arch12 zarch vx2 +-e700000000b8 vmsl VRR_VVVUU0V "vector multiply sum logical" arch12 zarch vx2 +-e700030000b8 vmslg VRR_VVVU0VB "vector multiply sum logical double word" arch12 zarch vx2 +-e7000000006c vnx VRR_VVV "vector not exclusive or" arch12 zarch vx2 ++e70000006004 vllezlf VRX_VRRD "vector load logical word element and zero - left aligned" arch12 zarch ++e700000000b8 vmsl VRR_VVVUU0V "vector multiply sum logical" arch12 zarch ++e700030000b8 vmslg VRR_VVVU0VB "vector multiply sum logical double word" arch12 zarch ++e7000000006c vnx VRR_VVV "vector not exclusive or" arch12 zarch + e7000000006e vnn VRR_VVV "vector nand" arch12 zarch +-e7000000006f voc VRR_VVV "vector or with complement" arch12 zarch vx2 +-e70000000050 vpopctb VRR_VV "vector population count byte" arch12 zarch vx2 +-e70000001050 vpopcth VRR_VV "vector population count halfword" arch12 zarch vx2 +-e70000002050 vpopctf VRR_VV "vector population count word" arch12 zarch vx2 +-e70000003050 vpopctg VRR_VV "vector population count double word" arch12 zarch vx2 +-e700000020e3 vfasb VRR_VVV "vector fp add short" arch12 zarch vx2 +-e700000820e3 wfasb VRR_VVV "scalar vector fp add scalar short" arch12 zarch vx2 +-e700000840e3 wfaxb VRR_VVV "scalar vector fp add scalar extended" arch12 zarch vx2 +-e700000020cb wfcsb VRR_VV "scalar vector fp compare scalar short" arch12 zarch vx2 +-e700000040cb wfcxb VRR_VV "scalar vector fp compare scalar extended" arch12 zarch vx2 +-e700000020ca wfksb VRR_VV "scalar vector fp compare and signal scalar short" arch12 zarch vx2 +-e700000040ca wfkxb VRR_VV "scalar vector fp compare and signal scalar extended" arch12 zarch vx2 ++e7000000006f voc VRR_VVV "vector or with complement" arch12 zarch ++e70000000050 vpopctb VRR_VV "vector population count byte" arch12 zarch ++e70000001050 vpopcth VRR_VV "vector population count halfword" arch12 zarch ++e70000002050 vpopctf VRR_VV "vector population count word" arch12 zarch ++e70000003050 vpopctg VRR_VV "vector population count double word" arch12 zarch ++e700000020e3 vfasb VRR_VVV "vector fp add short" arch12 zarch ++e700000820e3 wfasb VRR_VVV "scalar vector fp add scalar short" arch12 zarch ++e700000840e3 wfaxb VRR_VVV "scalar vector fp add scalar extended" arch12 zarch ++e700000020cb wfcsb VRR_VV "scalar vector fp compare scalar short" arch12 zarch ++e700000040cb wfcxb VRR_VV "scalar vector fp compare scalar extended" arch12 zarch ++e700000020ca wfksb VRR_VV "scalar vector fp compare and signal scalar short" arch12 zarch ++e700000040ca wfkxb VRR_VV "scalar vector fp compare and signal scalar extended" arch12 zarch + +-e700000020e8 vfcesb VRR_VVV "vector fp compare equal short" arch12 zarch vx2 +-e700001020e8 vfcesbs VRR_VVV "vector fp compare equal short" arch12 zarch vx2 +-e700000820e8 wfcesb VRR_VVV "scalar vector fp compare equal scalar short" arch12 zarch vx2 +-e700001820e8 wfcesbs VRR_VVV "scalar fp compare equal scalar short" arch12 zarch vx2 +-e700000840e8 wfcexb VRR_VVV "scalar vector fp compare equal scalar extended" arch12 zarch vx2 +-e700001840e8 wfcexbs VRR_VVV "scalar vector fp compare equal scalar extended" arch12 zarch vx2 ++e700000020e8 vfcesb VRR_VVV "vector fp compare equal short" arch12 zarch ++e700001020e8 vfcesbs VRR_VVV "vector fp compare equal short" arch12 zarch ++e700000820e8 wfcesb VRR_VVV "scalar vector fp compare equal scalar short" arch12 zarch ++e700001820e8 wfcesbs VRR_VVV "scalar fp compare equal scalar short" arch12 zarch ++e700000840e8 wfcexb VRR_VVV "scalar vector fp compare equal scalar extended" arch12 zarch ++e700001840e8 wfcexbs VRR_VVV "scalar vector fp compare equal scalar extended" arch12 zarch + +-e700000420e8 vfkesb VRR_VVV "vector fp compare and signal equal short" arch12 zarch vx2 +-e700001420e8 vfkesbs VRR_VVV "vector fp compare and signal equal short" arch12 zarch vx2 +-e700000c20e8 wfkesb VRR_VVV "scalar vector fp compare and signal equal scalar short" arch12 zarch vx2 +-e700001c20e8 wfkesbs VRR_VVV "scalar fp compare and signal equal scalar short" arch12 zarch vx2 ++e700000420e8 vfkesb VRR_VVV "vector fp compare and signal equal short" arch12 zarch ++e700001420e8 vfkesbs VRR_VVV "vector fp compare and signal equal short" arch12 zarch ++e700000c20e8 wfkesb VRR_VVV "scalar vector fp compare and signal equal scalar short" arch12 zarch ++e700001c20e8 wfkesbs VRR_VVV "scalar fp compare and signal equal scalar short" arch12 zarch + e700000430e8 vfkedb VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx + e700001430e8 vfkedbs VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx + e700000c30e8 wfkedb VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx + e700001c30e8 wfkedbs VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx +-e700000c40e8 wfkexb VRR_VVV "scalar vector fp compare and signal equal scalar extended" arch12 zarch vx2 +-e700001c40e8 wfkexbs VRR_VVV "scalar vector fp compare and signal equal scalar extended" arch12 zarch vx2 ++e700000c40e8 wfkexb VRR_VVV "scalar vector fp compare and signal equal scalar extended" arch12 zarch ++e700001c40e8 wfkexbs VRR_VVV "scalar vector fp compare and signal equal scalar extended" arch12 zarch + +-e700000020eb vfchsb VRR_VVV "vector fp compare high short" arch12 zarch vx2 +-e700001020eb vfchsbs VRR_VVV "vector fp compare high short" arch12 zarch vx2 +-e700000820eb wfchsb VRR_VVV "scalar vector fp compare high scalar short" arch12 zarch vx2 +-e700001820eb wfchsbs VRR_VVV "scalar vector fp compare high scalar short" arch12 zarch vx2 +-e700000840eb wfchxb VRR_VVV "scalar vector fp compare high scalar extended" arch12 zarch vx2 +-e700001840eb wfchxbs VRR_VVV "scalar vector fp compare high scalar extended" arch12 zarch vx2 ++e700000020eb vfchsb VRR_VVV "vector fp compare high short" arch12 zarch ++e700001020eb vfchsbs VRR_VVV "vector fp compare high short" arch12 zarch ++e700000820eb wfchsb VRR_VVV "scalar vector fp compare high scalar short" arch12 zarch ++e700001820eb wfchsbs VRR_VVV "scalar vector fp compare high scalar short" arch12 zarch ++e700000840eb wfchxb VRR_VVV "scalar vector fp compare high scalar extended" arch12 zarch ++e700001840eb wfchxbs VRR_VVV "scalar vector fp compare high scalar extended" arch12 zarch + +-e700000420eb vfkhsb VRR_VVV "vector fp compare and signal high short" arch12 zarch vx2 +-e700001420eb vfkhsbs VRR_VVV "vector fp compare and signal high short" arch12 zarch vx2 +-e700000c20eb wfkhsb VRR_VVV "scalar vector fp compare and signal high scalar short" arch12 zarch vx2 +-e700001c20eb wfkhsbs VRR_VVV "scalar vector fp compare and signal high scalar short" arch12 zarch vx2 ++e700000420eb vfkhsb VRR_VVV "vector fp compare and signal high short" arch12 zarch ++e700001420eb vfkhsbs VRR_VVV "vector fp compare and signal high short" arch12 zarch ++e700000c20eb wfkhsb VRR_VVV "scalar vector fp compare and signal high scalar short" arch12 zarch ++e700001c20eb wfkhsbs VRR_VVV "scalar vector fp compare and signal high scalar short" arch12 zarch + e700000430eb vfkhdb VRR_VVV "vector fp compare and signal high long" arch12 zarch vx + e700001430eb vfkhdbs VRR_VVV "vector fp compare and signal high long" arch12 zarch vx + e700000c30eb wfkhdb VRR_VVV "vector fp compare and signal high long" arch12 zarch vx + e700001c30eb wfkhdbs VRR_VVV "vector fp compare and signal high long" arch12 zarch vx +-e700000c40eb wfkhxb VRR_VVV "scalar vector fp compare and signal high scalar extended" arch12 zarch vx2 +-e700001c40eb wfkhxbs VRR_VVV "scalar vector fp compare and signal high scalar extended" arch12 zarch vx2 ++e700000c40eb wfkhxb VRR_VVV "scalar vector fp compare and signal high scalar extended" arch12 zarch ++e700001c40eb wfkhxbs VRR_VVV "scalar vector fp compare and signal high scalar extended" arch12 zarch + +-e700000020ea vfchesb VRR_VVV "vector fp compare high or equal short" arch12 zarch vx2 +-e700001020ea vfchesbs VRR_VVV "vector fp compare high or equal short" arch12 zarch vx2 +-e700000820ea wfchesb VRR_VVV "scalar vector fp compare high or equal scalar short" arch12 zarch vx2 +-e700001820ea wfchesbs VRR_VVV "scalar vector fp compare high or equal scalar short" arch12 zarch vx2 +-e700000840ea wfchexb VRR_VVV "scalar vector fp compare high or equal scalar extended" arch12 zarch vx2 +-e700001840ea wfchexbs VRR_VVV "scalar vector fp compare high or equal scalar extended" arch12 zarch vx2 ++e700000020ea vfchesb VRR_VVV "vector fp compare high or equal short" arch12 zarch ++e700001020ea vfchesbs VRR_VVV "vector fp compare high or equal short" arch12 zarch ++e700000820ea wfchesb VRR_VVV "scalar vector fp compare high or equal scalar short" arch12 zarch ++e700001820ea wfchesbs VRR_VVV "scalar vector fp compare high or equal scalar short" arch12 zarch ++e700000840ea wfchexb VRR_VVV "scalar vector fp compare high or equal scalar extended" arch12 zarch ++e700001840ea wfchexbs VRR_VVV "scalar vector fp compare high or equal scalar extended" arch12 zarch + +-e700000420ea vfkhesb VRR_VVV "vector fp compare and signal high or equal short" arch12 zarch vx2 +-e700001420ea vfkhesbs VRR_VVV "vector fp compare and signal high or equal short" arch12 zarch vx2 +-e700000c20ea wfkhesb VRR_VVV "scalar vector fp compare and signal high or equal scalar short" arch12 zarch vx2 +-e700001c20ea wfkhesbs VRR_VVV "scalar vector fp compare and signal high or equal scalar short" arch12 zarch vx2 ++e700000420ea vfkhesb VRR_VVV "vector fp compare and signal high or equal short" arch12 zarch ++e700001420ea vfkhesbs VRR_VVV "vector fp compare and signal high or equal short" arch12 zarch ++e700000c20ea wfkhesb VRR_VVV "scalar vector fp compare and signal high or equal scalar short" arch12 zarch ++e700001c20ea wfkhesbs VRR_VVV "scalar vector fp compare and signal high or equal scalar short" arch12 zarch + e700000430ea vfkhedb VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx + e700001430ea vfkhedbs VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx + e700000c30ea wfkhedb VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx + e700001c30ea wfkhedbs VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx +-e700000c40ea wfkhexb VRR_VVV "scalar vector fp compare and signal high or equal scalar extended" arch12 zarch vx2 +-e700001c40ea wfkhexbs VRR_VVV "scalar vector fp compare and signal high or equal scalar extended" arch12 zarch vx2 ++e700000c40ea wfkhexb VRR_VVV "scalar vector fp compare and signal high or equal scalar extended" arch12 zarch ++e700001c40ea wfkhexbs VRR_VVV "scalar vector fp compare and signal high or equal scalar extended" arch12 zarch + +-e700000020e5 vfdsb VRR_VVV "vector fp divide short" arch12 zarch vx2 +-e700000820e5 wfdsb VRR_VVV "scalar vector fp divide scalar short" arch12 zarch vx2 +-e700000840e5 wfdxb VRR_VVV "scalar vector fp divide scalar extended" arch12 zarch vx2 +-e700000020c7 vfisb VRR_VV0UU "vector load fp integer short" arch12 zarch vx2 +-e700000820c7 wfisb VRR_VV0UU8 "scalar vector load fp integer scalar short" arch12 zarch vx2 +-e700000840c7 wfixb VRR_VV0UU8 "scalar vector load fp integer scalar extended" arch12 zarch vx2 +-e700000000c4 vfll VRR_VV0UU2 "vector fp load lengthened" arch12 zarch vx2 +-e700000020c4 vflls VRR_VV "vector fp load lengthened" arch12 zarch vx2 +-e700000820c4 wflls VRR_VV "scalar vector fp load lengthened short" arch12 zarch vx2 +-e700000830c4 wflld VRR_VV "scalar vector fp load lengthened long" arch12 zarch vx2 +-e700000000c5 vflr VRR_VV0UUU "vector fp load rounded" arch12 zarch vx2 +-e700000030c5 vflrd VRR_VV0UU "vector fp load rounded long" arch12 zarch vx2 +-e700000830c5 wflrd VRR_VV0UU8 "scalar vector fp load rounded long" arch12 zarch vx2 +-e700000840c5 wflrx VRR_VV0UU8 "scalar vector fp load rounded extended" arch12 zarch vx2 +-e700000000ef vfmax VRR_VVV0UUU "vector fp maximum" arch12 zarch vx2 +-e700000020ef vfmaxsb VRR_VVV0U0 "vector fp maximum short" arch12 zarch vx2 +-e700000030ef vfmaxdb VRR_VVV0U0 "vector fp maximum long" arch12 zarch vx2 +-e700000820ef wfmaxsb VRR_VVV0U0 "scalar fp maximum scalar short" arch12 zarch vx2 +-e700000830ef wfmaxdb VRR_VVV0U0 "scalar fp maximum scalar long" arch12 zarch vx2 +-e700000840ef wfmaxxb VRR_VVV0U0 "scalar fp maximum scalar extended" arch12 zarch vx2 +-e700000000ee vfmin VRR_VVV0UUU "vector fp minimum" arch12 zarch vx2 +-e700000020ee vfminsb VRR_VVV0U0 "vector fp minimum short" arch12 zarch vx2 +-e700000030ee vfmindb VRR_VVV0U0 "vector fp minimum long" arch12 zarch vx2 +-e700000820ee wfminsb VRR_VVV0U0 "scalar fp minimum scalar short" arch12 zarch vx2 +-e700000830ee wfmindb VRR_VVV0U0 "scalar fp minimum scalar long" arch12 zarch vx2 +-e700000840ee wfminxb VRR_VVV0U0 "scalar fp minimum scalar extended" arch12 zarch vx2 +-e700000020e7 vfmsb VRR_VVV "vector fp multiply short" arch12 zarch vx2 +-e700000820e7 wfmsb VRR_VVV "scalar vector fp multiply scalar short" arch12 zarch vx2 +-e700000840e7 wfmxb VRR_VVV "scalar vector fp multiply scalar extended" arch12 zarch vx2 +-e7000200008f vfmasb VRR_VVVV "vector fp multiply and add short" arch12 zarch vx2 +-e7000208008f wfmasb VRR_VVVV "scalar vector fp multiply and add scalar short" arch12 zarch vx2 +-e7000408008f wfmaxb VRR_VVVV "scalar vector fp multiply and add scalar extended" arch12 zarch vx2 +-e7000200008e vfmssb VRR_VVVV "vector fp multiply and subtract short" arch12 zarch vx2 +-e7000208008e wfmssb VRR_VVVV "scalar vector fp multiply and subtract scalar short" arch12 zarch vx2 +-e7000408008e wfmsxb VRR_VVVV "scalar vector fp multiply and subtract scalar extended" arch12 zarch vx2 +-e7000000009f vfnma VRR_VVVU0UV "vector fp negative multiply and add" arch12 zarch vx2 +-e7000200009f vfnmasb VRR_VVVV "vector fp negative multiply and add short" arch12 zarch vx2 +-e7000208009f wfnmasb VRR_VVVV "scalar vector fp negative multiply and add scalar short" arch12 zarch vx2 +-e7000300009f vfnmadb VRR_VVVV "vector fp negative multiply and add long" arch12 zarch vx2 +-e7000308009f wfnmadb VRR_VVVV "scalar vector fp negative multiply and add scalar long" arch12 zarch vx2 +-e7000408009f wfnmaxb VRR_VVVV "scalar vector fp negative multiply and add scalar extended" arch12 zarch vx2 +-e7000000009e vfnms VRR_VVVU0UV "vector fp negative multiply and subtract" arch12 zarch vx2 +-e7000200009e vfnmssb VRR_VVVV "vector fp negative multiply and subtract short" arch12 zarch vx2 +-e7000208009e wfnmssb VRR_VVVV "scalar vector fp negative multiply and subtract scalar short" arch12 zarch vx2 +-e7000300009e vfnmsdb VRR_VVVV "vector fp negative multiply and subtract long" arch12 zarch vx2 +-e7000308009e wfnmsdb VRR_VVVV "scalar vector fp negative multiply and subtract scalar long" arch12 zarch vx2 +-e7000408009e wfnmsxb VRR_VVVV "scalar vector fp negative multiply and subtract scalar extended" arch12 zarch vx2 +-e700000020cc vfpsosb VRR_VV0U2 "vector fp perform sign operation short" arch12 zarch vx2 +-e700000820cc wfpsosb VRR_VV0U2 "scalar vector fp perform sign operation scalar short" arch12 zarch vx2 +-e700000020cc vflcsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2 +-e700000820cc wflcsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2 +-e700001020cc vflnsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2 +-e700001820cc wflnsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2 +-e700002020cc vflpsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2 +-e700002820cc wflpsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2 +-e700000840cc wfpsoxb VRR_VV0U2 "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2 +-e700000840cc wflcxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2 +-e700001840cc wflnxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2 +-e700002840cc wflpxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2 +-e700000020ce vfsqsb VRR_VV "vector fp square root short" arch12 zarch vx2 +-e700000820ce wfsqsb VRR_VV "scalar vector fp square root scalar short" arch12 zarch vx2 +-e700000840ce wfsqxb VRR_VV "scalar vector fp square root scalar extended" arch12 zarch vx2 +-e700000020e2 vfssb VRR_VVV "vector fp subtract short" arch12 zarch vx2 +-e700000820e2 wfssb VRR_VVV "scalar vector fp subtract scalar short" arch12 zarch vx2 +-e700000840e2 wfsxb VRR_VVV "scalar vector fp subtract scalar extended" arch12 zarch vx2 +-e7000000204a vftcisb VRI_VVU2 "vector fp test data class immediate short" arch12 zarch vx2 +-e7000008204a wftcisb VRI_VVU2 "scalar vector fp test data class immediate scalar short" arch12 zarch vx2 +-e7000008404a wftcixb VRI_VVU2 "scalar vector fp test data class immediate scalar extended" arch12 zarch vx2 ++e700000020e5 vfdsb VRR_VVV "vector fp divide short" arch12 zarch ++e700000820e5 wfdsb VRR_VVV "scalar vector fp divide scalar short" arch12 zarch ++e700000840e5 wfdxb VRR_VVV "scalar vector fp divide scalar extended" arch12 zarch ++e700000020c7 vfisb VRR_VV0UU "vector load fp integer short" arch12 zarch ++e700000820c7 wfisb VRR_VV0UU8 "scalar vector load fp integer scalar short" arch12 zarch ++e700000840c7 wfixb VRR_VV0UU8 "scalar vector load fp integer scalar extended" arch12 zarch ++e700000000c4 vfll VRR_VV0UU2 "vector fp load lengthened" arch12 zarch ++e700000020c4 vflls VRR_VV "vector fp load lengthened" arch12 zarch ++e700000820c4 wflls VRR_VV "scalar vector fp load lengthened short" arch12 zarch ++e700000830c4 wflld VRR_VV "scalar vector fp load lengthened long" arch12 zarch ++e700000000c5 vflr VRR_VV0UUU "vector fp load rounded" arch12 zarch ++e700000030c5 vflrd VRR_VV0UU "vector fp load rounded long" arch12 zarch ++e700000830c5 wflrd VRR_VV0UU8 "scalar vector fp load rounded long" arch12 zarch ++e700000840c5 wflrx VRR_VV0UU8 "scalar vector fp load rounded extended" arch12 zarch ++e700000000ef vfmax VRR_VVV0UUU "vector fp maximum" arch12 zarch ++e700000020ef vfmaxsb VRR_VVV0U0 "vector fp maximum short" arch12 zarch ++e700000030ef vfmaxdb VRR_VVV0U0 "vector fp maximum long" arch12 zarch ++e700000820ef wfmaxsb VRR_VVV0U0 "scalar fp maximum scalar short" arch12 zarch ++e700000830ef wfmaxdb VRR_VVV0U0 "scalar fp maximum scalar long" arch12 zarch ++e700000840ef wfmaxxb VRR_VVV0U0 "scalar fp maximum scalar extended" arch12 zarch ++e700000000ee vfmin VRR_VVV0UUU "vector fp minimum" arch12 zarch ++e700000020ee vfminsb VRR_VVV0U0 "vector fp minimum short" arch12 zarch ++e700000030ee vfmindb VRR_VVV0U0 "vector fp minimum long" arch12 zarch ++e700000820ee wfminsb VRR_VVV0U0 "scalar fp minimum scalar short" arch12 zarch ++e700000830ee wfmindb VRR_VVV0U0 "scalar fp minimum scalar long" arch12 zarch ++e700000840ee wfminxb VRR_VVV0U0 "scalar fp minimum scalar extended" arch12 zarch ++e700000020e7 vfmsb VRR_VVV "vector fp multiply short" arch12 zarch ++e700000820e7 wfmsb VRR_VVV "scalar vector fp multiply scalar short" arch12 zarch ++e700000840e7 wfmxb VRR_VVV "scalar vector fp multiply scalar extended" arch12 zarch ++e7000200008f vfmasb VRR_VVVV "vector fp multiply and add short" arch12 zarch ++e7000208008f wfmasb VRR_VVVV "scalar vector fp multiply and add scalar short" arch12 zarch ++e7000408008f wfmaxb VRR_VVVV "scalar vector fp multiply and add scalar extended" arch12 zarch ++e7000200008e vfmssb VRR_VVVV "vector fp multiply and subtract short" arch12 zarch ++e7000208008e wfmssb VRR_VVVV "scalar vector fp multiply and subtract scalar short" arch12 zarch ++e7000408008e wfmsxb VRR_VVVV "scalar vector fp multiply and subtract scalar extended" arch12 zarch ++e7000000009f vfnma VRR_VVVU0UV "vector fp negative multiply and add" arch12 zarch ++e7000200009f vfnmasb VRR_VVVV "vector fp negative multiply and add short" arch12 zarch ++e7000208009f wfnmasb VRR_VVVV "scalar vector fp negative multiply and add scalar short" arch12 zarch ++e7000300009f vfnmadb VRR_VVVV "vector fp negative multiply and add long" arch12 zarch ++e7000308009f wfnmadb VRR_VVVV "scalar vector fp negative multiply and add scalar long" arch12 zarch ++e7000408009f wfnmaxb VRR_VVVV "scalar vector fp negative multiply and add scalar extended" arch12 zarch ++e7000000009e vfnms VRR_VVVU0UV "vector fp negative multiply and subtract" arch12 zarch ++e7000200009e vfnmssb VRR_VVVV "vector fp negative multiply and subtract short" arch12 zarch ++e7000208009e wfnmssb VRR_VVVV "scalar vector fp negative multiply and subtract scalar short" arch12 zarch ++e7000300009e vfnmsdb VRR_VVVV "vector fp negative multiply and subtract long" arch12 zarch ++e7000308009e wfnmsdb VRR_VVVV "scalar vector fp negative multiply and subtract scalar long" arch12 zarch ++e7000408009e wfnmsxb VRR_VVVV "scalar vector fp negative multiply and subtract scalar extended" arch12 zarch ++e700000020cc vfpsosb VRR_VV0U2 "vector fp perform sign operation short" arch12 zarch ++e700000820cc wfpsosb VRR_VV0U2 "scalar vector fp perform sign operation scalar short" arch12 zarch ++e700000020cc vflcsb VRR_VV "vector fp perform sign operation short" arch12 zarch ++e700000820cc wflcsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch ++e700001020cc vflnsb VRR_VV "vector fp perform sign operation short" arch12 zarch ++e700001820cc wflnsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch ++e700002020cc vflpsb VRR_VV "vector fp perform sign operation short" arch12 zarch ++e700002820cc wflpsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch ++e700000840cc wfpsoxb VRR_VV0U2 "scalar vector fp perform sign operation scalar extended" arch12 zarch ++e700000840cc wflcxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch ++e700001840cc wflnxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch ++e700002840cc wflpxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch ++e700000020ce vfsqsb VRR_VV "vector fp square root short" arch12 zarch ++e700000820ce wfsqsb VRR_VV "scalar vector fp square root scalar short" arch12 zarch ++e700000840ce wfsqxb VRR_VV "scalar vector fp square root scalar extended" arch12 zarch ++e700000020e2 vfssb VRR_VVV "vector fp subtract short" arch12 zarch ++e700000820e2 wfssb VRR_VVV "scalar vector fp subtract scalar short" arch12 zarch ++e700000840e2 wfsxb VRR_VVV "scalar vector fp subtract scalar extended" arch12 zarch ++e7000000204a vftcisb VRI_VVU2 "vector fp test data class immediate short" arch12 zarch ++e7000008204a wftcisb VRI_VVU2 "scalar vector fp test data class immediate scalar short" arch12 zarch ++e7000008404a wftcixb VRI_VVU2 "scalar vector fp test data class immediate scalar extended" arch12 zarch + + # Miscellaneous Instruction Extensions Facility 2 + +@@ -1843,28 +1843,28 @@ e30000000039 sgh RXY_RRRD "subtract halfword from 64 bit value" arch12 zarch + + # Vector packed decimal facility + +-e60000000037 vlrlr VRS_RRDV "vector load rightmost with length" arch12 zarch vx2 +-e60000000035 vlrl VSI_URDV "vector load rightmost with immediate length" arch12 zarch vx2 +-e6000000003f vstrlr VRS_RRDV "vector store rightmost with length" arch12 zarch vx2 +-e6000000003d vstrl VSI_URDV "vector store rightmost with immediate length" arch12 zarch vx2 +-e60000000071 vap VRI_VVV0UU2 "vector add decimal" arch12 zarch vx2 +-e60000000077 vcp VRR_0VV0U "vector compare decimal" arch12 zarch vx2 +-e60000000050 vcvb VRR_RV0U "vector convert to binary 32 bit" arch12 zarch vx2 +-e60000000052 vcvbg VRR_RV0U "vector convert to binary 64 bit" arch12 zarch vx2 +-e60000000058 vcvd VRI_VR0UU "vector convert to decimal 32 bit" arch12 zarch vx2 +-e6000000005a vcvdg VRI_VR0UU "vector convert to decimal 64 bit" arch12 zarch vx2 +-e6000000007a vdp VRI_VVV0UU2 "vector divide decimal" arch12 zarch vx2 +-e60000000049 vlip VRI_V0UU2 "vector load immediate decimal" arch12 zarch vx2 +-e60000000078 vmp VRI_VVV0UU2 "vector multiply decimal" arch12 zarch vx2 +-e60000000079 vmsp VRI_VVV0UU2 "vector multiply and shift decimal" arch12 zarch vx2 +-e60000000034 vpkz VSI_URDV "vector pack zoned" arch12 zarch vx2 +-e6000000005b vpsop VRI_VVUUU2 "vector perform sign operation decimal" arch12 zarch vx2 +-e6000000007b vrp VRI_VVV0UU2 "vector remainder decimal" arch12 zarch vx2 +-e6000000007e vsdp VRI_VVV0UU2 "vector shift and divide decimal" arch12 zarch vx2 +-e60000000059 vsrp VRI_VVUUU2 "vector shift and round decimal" arch12 zarch vx2 +-e60000000073 vsp VRI_VVV0UU2 "vector subtract decimal" arch12 zarch vx2 +-e6000000005f vtp VRR_0V "vector test decimal" arch12 zarch vx2 +-e6000000003c vupkz VSI_URDV "vector unpack zoned" arch12 zarch vx2 ++e60000000037 vlrlr VRS_RRDV "vector load rightmost with length" arch12 zarch ++e60000000035 vlrl VSI_URDV "vector load rightmost with immediate length" arch12 zarch ++e6000000003f vstrlr VRS_RRDV "vector store rightmost with length" arch12 zarch ++e6000000003d vstrl VSI_URDV "vector store rightmost with immediate length" arch12 zarch ++e60000000071 vap VRI_VVV0UU2 "vector add decimal" arch12 zarch ++e60000000077 vcp VRR_0VV0U "vector compare decimal" arch12 zarch ++e60000000050 vcvb VRR_RV0U "vector convert to binary 32 bit" arch12 zarch ++e60000000052 vcvbg VRR_RV0U "vector convert to binary 64 bit" arch12 zarch ++e60000000058 vcvd VRI_VR0UU "vector convert to decimal 32 bit" arch12 zarch ++e6000000005a vcvdg VRI_VR0UU "vector convert to decimal 64 bit" arch12 zarch ++e6000000007a vdp VRI_VVV0UU2 "vector divide decimal" arch12 zarch ++e60000000049 vlip VRI_V0UU2 "vector load immediate decimal" arch12 zarch ++e60000000078 vmp VRI_VVV0UU2 "vector multiply decimal" arch12 zarch ++e60000000079 vmsp VRI_VVV0UU2 "vector multiply and shift decimal" arch12 zarch ++e60000000034 vpkz VSI_URDV "vector pack zoned" arch12 zarch ++e6000000005b vpsop VRI_VVUUU2 "vector perform sign operation decimal" arch12 zarch ++e6000000007b vrp VRI_VVV0UU2 "vector remainder decimal" arch12 zarch ++e6000000007e vsdp VRI_VVV0UU2 "vector shift and divide decimal" arch12 zarch ++e60000000059 vsrp VRI_VVUUU2 "vector shift and round decimal" arch12 zarch ++e60000000073 vsp VRI_VVV0UU2 "vector subtract decimal" arch12 zarch ++e6000000005f vtp VRR_0V "vector test decimal" arch12 zarch ++e6000000003c vupkz VSI_URDV "vector unpack zoned" arch12 zarch + + # Guarded storage facility + diff --git a/binutils.changes b/binutils.changes index accb556..e618bd8 100644 --- a/binutils.changes +++ b/binutils.changes @@ -1,3 +1,10 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + ------------------------------------------------------------------- Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com diff --git a/binutils.spec b/binutils.spec index 3b20208..56f4082 100644 --- a/binutils.spec +++ b/binutils.spec @@ -248,6 +248,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-aarch64-binutils.changes b/cross-aarch64-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-aarch64-binutils.changes +++ b/cross-aarch64-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-aarch64-binutils.spec b/cross-aarch64-binutils.spec index 8972102..7e65c62 100644 --- a/cross-aarch64-binutils.spec +++ b/cross-aarch64-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-arm-binutils.changes b/cross-arm-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-arm-binutils.changes +++ b/cross-arm-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-arm-binutils.spec b/cross-arm-binutils.spec index 7e069e4..8b9932e 100644 --- a/cross-arm-binutils.spec +++ b/cross-arm-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-avr-binutils.changes b/cross-avr-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-avr-binutils.changes +++ b/cross-avr-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-avr-binutils.spec b/cross-avr-binutils.spec index e5f541e..19533aa 100644 --- a/cross-avr-binutils.spec +++ b/cross-avr-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-epiphany-binutils.changes b/cross-epiphany-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-epiphany-binutils.changes +++ b/cross-epiphany-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-epiphany-binutils.spec b/cross-epiphany-binutils.spec index d61b341..7147eb0 100644 --- a/cross-epiphany-binutils.spec +++ b/cross-epiphany-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-hppa-binutils.changes b/cross-hppa-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-hppa-binutils.changes +++ b/cross-hppa-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-hppa-binutils.spec b/cross-hppa-binutils.spec index c61fb5b..2237681 100644 --- a/cross-hppa-binutils.spec +++ b/cross-hppa-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-hppa64-binutils.changes b/cross-hppa64-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-hppa64-binutils.changes +++ b/cross-hppa64-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-hppa64-binutils.spec b/cross-hppa64-binutils.spec index 9f5465e..e46864e 100644 --- a/cross-hppa64-binutils.spec +++ b/cross-hppa64-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-i386-binutils.changes b/cross-i386-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-i386-binutils.changes +++ b/cross-i386-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-i386-binutils.spec b/cross-i386-binutils.spec index fb210bd..92928ce 100644 --- a/cross-i386-binutils.spec +++ b/cross-i386-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-ia64-binutils.changes b/cross-ia64-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-ia64-binutils.changes +++ b/cross-ia64-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-ia64-binutils.spec b/cross-ia64-binutils.spec index c9837e3..b6af7e3 100644 --- a/cross-ia64-binutils.spec +++ b/cross-ia64-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-m68k-binutils.changes b/cross-m68k-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-m68k-binutils.changes +++ b/cross-m68k-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-m68k-binutils.spec b/cross-m68k-binutils.spec index 49b11bd..7a8fb07 100644 --- a/cross-m68k-binutils.spec +++ b/cross-m68k-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-mips-binutils.changes b/cross-mips-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-mips-binutils.changes +++ b/cross-mips-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-mips-binutils.spec b/cross-mips-binutils.spec index b438c86..1de6293 100644 --- a/cross-mips-binutils.spec +++ b/cross-mips-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-ppc-binutils.changes b/cross-ppc-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-ppc-binutils.changes +++ b/cross-ppc-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-ppc-binutils.spec b/cross-ppc-binutils.spec index dd93b91..50910cc 100644 --- a/cross-ppc-binutils.spec +++ b/cross-ppc-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-ppc64-binutils.changes b/cross-ppc64-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-ppc64-binutils.changes +++ b/cross-ppc64-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-ppc64-binutils.spec b/cross-ppc64-binutils.spec index f8d90ce..b4410d8 100644 --- a/cross-ppc64-binutils.spec +++ b/cross-ppc64-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-ppc64le-binutils.changes b/cross-ppc64le-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-ppc64le-binutils.changes +++ b/cross-ppc64le-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-ppc64le-binutils.spec b/cross-ppc64le-binutils.spec index 40e9411..623152b 100644 --- a/cross-ppc64le-binutils.spec +++ b/cross-ppc64le-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-rx-binutils.changes b/cross-rx-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-rx-binutils.changes +++ b/cross-rx-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-rx-binutils.spec b/cross-rx-binutils.spec index 831e1d6..d287546 100644 --- a/cross-rx-binutils.spec +++ b/cross-rx-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-s390-binutils.changes b/cross-s390-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-s390-binutils.changes +++ b/cross-s390-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-s390-binutils.spec b/cross-s390-binutils.spec index 4d5cd21..f767792 100644 --- a/cross-s390-binutils.spec +++ b/cross-s390-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-s390x-binutils.changes b/cross-s390x-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-s390x-binutils.changes +++ b/cross-s390x-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-s390x-binutils.spec b/cross-s390x-binutils.spec index 29e0bbd..498f3ce 100644 --- a/cross-s390x-binutils.spec +++ b/cross-s390x-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-sparc-binutils.changes b/cross-sparc-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-sparc-binutils.changes +++ b/cross-sparc-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-sparc-binutils.spec b/cross-sparc-binutils.spec index 832bccb..0b35bb7 100644 --- a/cross-sparc-binutils.spec +++ b/cross-sparc-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-sparc64-binutils.changes b/cross-sparc64-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-sparc64-binutils.changes +++ b/cross-sparc64-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-sparc64-binutils.spec b/cross-sparc64-binutils.spec index 9fd8819..00d04ab 100644 --- a/cross-sparc64-binutils.spec +++ b/cross-sparc64-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-spu-binutils.changes b/cross-spu-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-spu-binutils.changes +++ b/cross-spu-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-spu-binutils.spec b/cross-spu-binutils.spec index 58eb57d..bc0aa27 100644 --- a/cross-spu-binutils.spec +++ b/cross-spu-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers diff --git a/cross-x86_64-binutils.changes b/cross-x86_64-binutils.changes index a4f65a5..e618bd8 100644 --- a/cross-x86_64-binutils.changes +++ b/cross-x86_64-binutils.changes @@ -1,3 +1,17 @@ +------------------------------------------------------------------- +Fri Mar 31 10:30:08 UTC 2017 - rguenther@suse.com + +- Update binutils-2.28-branch.diff. +- Make compressed debug section handling explicit, disable for + old products and enable for gas on all architectures otherwise. + +------------------------------------------------------------------- +Thu Mar 30 11:16:18 UTC 2017 - rguenther@suse.com + +- Remove empty rpath component removal optimization from + binutils-skip-rpaths.patch to workaround CMake rpath handling. + [boo#1025282] + ------------------------------------------------------------------- Fri Mar 17 15:28:26 UTC 2017 - matz@suse.com diff --git a/cross-x86_64-binutils.spec b/cross-x86_64-binutils.spec index d33c6af..3374213 100644 --- a/cross-x86_64-binutils.spec +++ b/cross-x86_64-binutils.spec @@ -251,6 +251,10 @@ cd build-dir %endif %if %{suse_version} <= 1320 --disable-x86-relax-relocations \ + --disable-compressed-debug-sections \ +%endif +%if %{suse_version} > 1320 + --enable-compressed-debug-sections=gas \ %endif --enable-shared make %{?_smp_mflags} all-bfd TARGET-bfd=headers