Nicer changelog.

OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=473

binutils.changes

@@ -6,21 +6,23 @@ Tue Aug  6 14:09:24 UTC 2024 - Michael Matz <matz@suse.com>
   * Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF
     (APX_F now fully supported)
   * x86 Intel syntax now warns about more mnemonic suffixes
-* macros and .irp/.irpc/.rept bodies can use \+ to get at number of times
+  * macros and .irp/.irpc/.rept bodies can use \+ to get at number
-  the macro/body was executed
+    of times the macro/body was executed
-* aarch64: support 'armv9.5-a' for -march, add support for LUT and LUT2
+  * aarch64: support 'armv9.5-a' for -march, add support for LUT
-* s390: base register operand in D(X,B) and D(L,B) can now be omitted
+    and LUT2
-  (ala 'D(X,)'); warn when register type doesn't match operand type
+  * s390: base register operand in D(X,B) and D(L,B) can now be
-  (use option 'warn-regtype-mismatch=[strict|relaxed|no]' to adjust)
+    omitted (ala 'D(X,)'); warn when register type doesn't match
-* riscv: support various extensions: Zacas, Zcmp, Zfbfmin, Zvfbfmin,
+    operand type (use option
-  Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw, XSfCease, all at
+    'warn-regtype-mismatch=[strict|relaxed|no]' to adjust)
-  version 1.0;
+  * riscv: support various extensions: Zacas, Zcmp, Zfbfmin,
-  remove support for assembly of privileged spec 1.9.1 (linking support
+    Zvfbfmin, Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw,
-  remains)
+    XSfCease, all at version 1.0;
+    remove support for assembly of privileged spec 1.9.1 (linking
+    support remains)
   * arm: remove support for some old co-processors: Maverick and FPA
-* mips: '--trap' now causes either trap or breakpoint instructions to
+  * mips: '--trap' now causes either trap or breakpoint instructions
-  be emitted as per current ISA, instead of always using trap insn
+    to be emitted as per current ISA, instead of always using trap
-  and failing when current ISA was incompatible with that
+    insn and failing when current ISA was incompatible with that
   * LoongArch: accept .option pseudo-op for fine-grained control
     of assembly code options; add support for DT_RELR
   * readelf: now displays RELR relocations in full detail;
@@ -28,21 +30,23 @@ Tue Aug  6 14:09:24 UTC 2024 - Michael Matz <matz@suse.com>
     according to their type
   * objdump/readelf now dump also .eh_frame_hdr (when present) when
     dumping .eh_frame
-* gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake processors;
+  * gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake
-  add minimal support for riscv
+    processors; add minimal support for riscv
   * linker:
     - put .got and .got.plt into relro segment
     - add -z isa-level-report=[none|all|needed|used] to the x86 ELF
       linker to report needed and used x86-64 ISA levels
-  - add --rosegment option which changes the -z separate-code option
+    - add --rosegment option which changes the -z separate-code
-    so that only one read-only segment is created (instead of two)
+      option so that only one read-only segment is created (instead
-  - add --section-ordering-file <FILE> option to add extra mapping
+      of two)
-    of input sections to output sections
+    - add --section-ordering-file <FILE> option to add extra
-  - add -plugin-save-temps to store plugin intermediate files permanently
+      mapping of input sections to output sections
-* Removed binutils-2.42.tar.bz2, binutils-2.42-branch.diff.gz.
+    - add -plugin-save-temps to store plugin intermediate files
-* Added binutils-2.43.tar.bz2, binutils-2.43-branch.diff.gz.
+      permanently
-* Removed upstream patch riscv-no-relax.patch.
+- Removed binutils-2.42.tar.bz2, binutils-2.42-branch.diff.gz.
-* Rebased ld-relro.diff and binutils-revert-rela.diff.
+- Added binutils-2.43.tar.bz2, binutils-2.43-branch.diff.gz.
+- Removed upstream patch riscv-no-relax.patch.
+- Rebased ld-relro.diff and binutils-revert-rela.diff.
 
 -------------------------------------------------------------------
 Thu Jun 13 08:35:38 UTC 2024 - Andreas Schwab <schwab@suse.de>