- Adjust cross-avr-omit_section_dynsym.patch.

OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=280
2018-07-16 11:21:50 +00:00 · 2018-07-16 11:21:50 +00:00 · 5d3575eaf0
commit 5d3575eaf0
parent 6178497ff2
23 changed files with 23 additions and 1 deletions
--- a/binutils.changes
+++ b/binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-aarch64-binutils.changes
+++ b/cross-aarch64-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-arm-binutils.changes
+++ b/cross-arm-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-avr-binutils.changes
+++ b/cross-avr-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-avr-omit_section_dynsym.patch
+++ b/cross-avr-omit_section_dynsym.patch
@ -12,7 +12,7 @@ diff -c -3 -p -r1.27 elf32-avr.c
  					bfd_elf_avr_final_write_processing
  #define elf_backend_object_p		elf32_avr_object_p
 + #define elf_backend_omit_section_dynsym \
-+   ((bfd_boolean (*) (bfd *, struct bfd_link_info *, asection *)) bfd_true)
+   _bfd_elf_omit_section_dynsym_all
  
  #define bfd_elf32_bfd_relax_section elf32_avr_relax_section
  #define bfd_elf32_bfd_get_relocated_section_contents \
--- a/cross-epiphany-binutils.changes
+++ b/cross-epiphany-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-hppa-binutils.changes
+++ b/cross-hppa-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-hppa64-binutils.changes
+++ b/cross-hppa64-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-i386-binutils.changes
+++ b/cross-i386-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-ia64-binutils.changes
+++ b/cross-ia64-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-m68k-binutils.changes
+++ b/cross-m68k-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-mips-binutils.changes
+++ b/cross-mips-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-ppc-binutils.changes
+++ b/cross-ppc-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-ppc64-binutils.changes
+++ b/cross-ppc64-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-ppc64le-binutils.changes
+++ b/cross-ppc64le-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-riscv64-binutils.changes
+++ b/cross-riscv64-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-rx-binutils.changes
+++ b/cross-rx-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-s390-binutils.changes
+++ b/cross-s390-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-s390x-binutils.changes
+++ b/cross-s390x-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-sparc-binutils.changes
+++ b/cross-sparc-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-sparc64-binutils.changes
+++ b/cross-sparc64-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-spu-binutils.changes
+++ b/cross-spu-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de
--- a/cross-x86_64-binutils.changes
+++ b/cross-x86_64-binutils.changes
@ -30,6 +30,7 @@ Mon Jul 16 07:55:51 UTC 2018 - rguenther@suse.com
  * Includes riscv-relax-size.patch, riscv-relax-relocatable.patch,
    riscv-relax-versioned-hidden.patch and riscv-wrap-relax.patch
 - Refresh enable-targets-gold.diff.
+- Adjust cross-avr-omit_section_dynsym.patch.

 -------------------------------------------------------------------
 Mon Jun  4 09:49:37 UTC 2018 - schwab@suse.de