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Accepting request 568059 from home:Andreas_Schwab:Factory

Browse Source 
- Add riscv64 to %target_list

OBS-URL: https://build.opensuse.org/request/show/568059
OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=261
This commit is contained in:
Michael Matz 2018-01-22 15:21:29 +00:00 committed by Git OBS Bridge
parent 02edc8adef
commit 9cdc0d3b6d
44 changed files with 132 additions and 22 deletions
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5
binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
binutils.spec
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@ -63,7 +63,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-aarch64-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-aarch64-binutils.spec
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@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-arm-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-arm-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-avr-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-avr-binutils.spec
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@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-epiphany-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-epiphany-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-hppa-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-hppa-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-hppa64-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-hppa64-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-i386-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-i386-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-ia64-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-ia64-binutils.spec
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@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-m68k-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-m68k-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-mips-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-mips-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-ppc-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-ppc-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-ppc64-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-ppc64-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-ppc64le-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-ppc64le-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-riscv64-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-riscv64-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-rx-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-rx-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-s390-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-s390-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-s390x-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-s390x-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-sparc-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-sparc-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-sparc64-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-sparc64-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-spu-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-spu-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#

5
cross-x86_64-binutils.changes
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@ -1,3 +1,8 @@
-------------------------------------------------------------------
Mon Jan 22 09:40:25 UTC 2018 - schwab@suse.de
- Add riscv64 to %target_list
-------------------------------------------------------------------
Wed Jan 17 11:28:03 UTC 2018 - afaerber@suse.de

2
cross-x86_64-binutils.spec
View File

@ -66,7 +66,7 @@ Release: 0
%else
%define build_multitarget 0
%endif
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le s390 s390x sh4 sparc sparc64 x86_64
%define target_list aarch64 alpha armv5l armv6l armv7l armv8l hppa hppa64 i686 ia64 m68k mips powerpc powerpc64 powerpc64le riscv64 s390 s390x sh4 sparc sparc64 x86_64
#
#
#