diff --git a/binutils-2.26-branch.diff b/binutils-2.26-branch.diff index 8275909..80d25a8 100644 --- a/binutils-2.26-branch.diff +++ b/binutils-2.26-branch.diff @@ -1,8 +1,85 @@ diff --git a/bfd/ChangeLog b/bfd/ChangeLog -index e860c3e..4741b19 100644 +index e860c3e..6d70417 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog -@@ -1,3 +1,156 @@ +@@ -1,3 +1,233 @@ ++2016-06-09 Alan Modra ++ ++ PR ld/20159 ++ PR ld/16467 ++ * elflink.c (_bfd_elf_merge_symbol): Revert PR16467 change. ++ (_bfd_elf_add_default_symbol): Don't indirect to/from defined ++ symbol given a version by a script different to the version ++ of the symbol being added. ++ (elf_link_add_object_symbols): Use _bfd_elf_strtab_save and ++ _bfd_elf_strtab_restore. Don't fudge dynstr references. ++ * elf-strtab.c (_bfd_elf_strtab_restore_size): Delete. ++ (struct strtab_save): New. ++ (_bfd_elf_strtab_save, _bfd_elf_strtab_restore): New functions. ++ * elf-bfd.h (_bfd_elf_strtab_restore_size): Delete. ++ (_bfd_elf_strtab_save, _bfd_elf_strtab_restore): Declare. ++ ++2016-05-20 H.J. Lu ++ ++ Backport from master ++ 2016-05-20 H.J. Lu ++ ++ * elf32-i386.c (elf_i386_check_relocs): Don't check R_386_GOT32 ++ when setting need_convert_load. ++ ++ 2016-05-19 H.J. Lu ++ ++ PR ld/20117 ++ * elf32-i386.c (elf_i386_convert_load): Don't convert ++ R_386_GOT32. ++ ++2016-05-18 Christophe Monat ++ ++ Backport from master ++ 2016-05-09 Christophe Monat ++ ++ PR ld/20030 ++ * elf32-arm.c (is_thumb2_vldm): Account for T1 (DP) encoding. ++ (stm32l4xx_need_create_replacing_stub): Rename ambiguous nb_regs ++ to nb_words. ++ (create_instruction_vldmia): Add is_dp to disambiguate SP/DP ++ encoding. ++ (create_instruction_vldmdb): Likewise. ++ (stm32l4xx_create_replacing_stub_vldm): is_dp detects DP encoding, ++ uses it to re-encode. ++ ++2016-05-15 H.J. Lu ++ ++ Backport from master ++ 2016-05-13 H.J. Lu ++ ++ PR ld/20093 ++ * elf64-x86-64.c (elf_x86_64_convert_load_reloc): Don't convert ++ GOTPCREL relocation against large section. ++ ++ * elflink.c (bfd_elf_final_link): Likewise. ++ ++2016-05-11 Alan Modra ++ ++ PR 20060 ++ * elf64-ppc.c (ppc64_elf_tls_setup): Clear forced_local. ++ * elf32-ppc.c (ppc_elf_tls_setup): Likewise. ++ ++2016-04-30 H.J. Lu ++ ++ Backport from master ++ 2016-04-27 H.J. Lu ++ ++ PR ld/20006 ++ * elf64-x86-64.c (elf_x86_64_convert_load): Skip debug sections ++ when estimating distances between output sections. ++ ++2016-03-29 Toni Spets ++ ++ PR 19878 ++ * coffcode.h (coff_write_object_contents): Revert accidental ++ 2014-11-10 change. ++ +2016-03-17 H.J. Lu + + Backport from master @@ -159,7 +236,7 @@ index e860c3e..4741b19 100644 2016-01-25 Tristan Gingold * version.m4: Bump version to 2.26 -@@ -119,7 +272,7 @@ +@@ -119,7 +349,7 @@ * configure: Regenerate. 2015-11-11 Alan Modra @@ -168,7 +245,7 @@ index e860c3e..4741b19 100644 * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. -@@ -179,8 +332,8 @@ +@@ -179,8 +409,8 @@ 2015-10-29 Catherine Moore @@ -179,7 +256,7 @@ index e860c3e..4741b19 100644 2015-10-29 Ed Schouten -@@ -232,7 +385,7 @@ +@@ -232,7 +462,7 @@ * bfd-in2.h: Regenerate. 2015-10-27 Laurent Alfonsi @@ -188,7 +265,7 @@ index e860c3e..4741b19 100644 * bfd-in2.h: Regenerate. * bfd-in.h (bfd_arm_stm32l4xx_fix): New enum. Specify how -@@ -1225,115 +1378,115 @@ +@@ -1225,115 +1455,115 @@ 2015-08-18 H.J. Lu @@ -411,7 +488,7 @@ index e860c3e..4741b19 100644 2015-08-18 Alan Modra -@@ -1387,7 +1540,7 @@ +@@ -1387,7 +1617,7 @@ 2015-08-11 Jiong Wang @@ -420,7 +497,7 @@ index e860c3e..4741b19 100644 Loose the check for symbol from ABS section. (elfNN_aarch64_size_stubs): Pass sym_sec. -@@ -1688,10 +1841,10 @@ +@@ -1688,10 +1918,10 @@ 2015-07-10 H.J. Lu @@ -435,7 +512,7 @@ index e860c3e..4741b19 100644 2015-07-09 Catherine Moore -@@ -2004,7 +2157,6 @@ +@@ -2004,7 +2234,6 @@ Bernd Schmidt Paul Brook @@ -443,7 +520,7 @@ index e860c3e..4741b19 100644 * bfd-in2.h: Regenerated. * elf-bfd.h (DWARF2_EH_HDR, COMPACT_EH_HDR): Define. (COMPACT_EH_CANT_UNWIND_OPCODE): Define. -@@ -2913,7 +3065,7 @@ +@@ -2913,7 +3142,7 @@ 2015-03-18 H.J. Lu * compress.c (bfd_compress_section_contents): Make it static. @@ -452,7 +529,7 @@ index e860c3e..4741b19 100644 2015-03-18 Eric Youngdale -@@ -3062,8 +3214,8 @@ +@@ -3062,8 +3291,8 @@ 2015-02-27 Marcus Shawcroft @@ -463,7 +540,7 @@ index e860c3e..4741b19 100644 2015-02-26 Marcus Shawcroft -@@ -3534,7 +3686,7 @@ +@@ -3534,7 +3763,7 @@ is weak or pointer_equality_needed is FALSE. * elf32-arm.c (elf32_arm_finish_dynamic_symbol): Improve @@ -690,6 +767,19 @@ index 4e6420a..9d7c845 100644 /* Now let bfd_perform_relocation finish everything up. */ return bfd_reloc_continue; +diff --git a/bfd/coffcode.h b/bfd/coffcode.h +index 2499885..97db5f7 100644 +--- a/bfd/coffcode.h ++++ b/bfd/coffcode.h +@@ -4076,6 +4076,8 @@ coff_write_object_contents (bfd * abfd) + internal_f.f_flags |= F_DYNLOAD; + #endif + ++ memset (&internal_a, 0, sizeof internal_a); ++ + /* Set up architecture-dependent stuff. */ + { + unsigned int magic = 0; diff --git a/bfd/cofflink.c b/bfd/cofflink.c index 8d98fec..88eb2b3 100644 --- a/bfd/cofflink.c @@ -809,6 +899,294 @@ index 176f018..64cfe9b 100644 || (msec = find_debug_info (debug_bfd, debug_sections, NULL)) == NULL || !bfd_generic_link_read_symbols (debug_bfd)) +diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h +index 70e3327..f36b945 100644 +--- a/bfd/elf-bfd.h ++++ b/bfd/elf-bfd.h +@@ -2039,9 +2039,11 @@ extern void _bfd_elf_strtab_delref + extern unsigned int _bfd_elf_strtab_refcount + (struct elf_strtab_hash *, bfd_size_type); + extern void _bfd_elf_strtab_clear_all_refs +- (struct elf_strtab_hash *tab); +-extern void _bfd_elf_strtab_restore_size +- (struct elf_strtab_hash *, bfd_size_type); ++ (struct elf_strtab_hash *); ++extern void *_bfd_elf_strtab_save ++ (struct elf_strtab_hash *); ++extern void _bfd_elf_strtab_restore ++ (struct elf_strtab_hash *, void *); + extern bfd_size_type _bfd_elf_strtab_size + (struct elf_strtab_hash *); + extern bfd_size_type _bfd_elf_strtab_offset +diff --git a/bfd/elf-strtab.c b/bfd/elf-strtab.c +index 4d38e04..e7de973 100644 +--- a/bfd/elf-strtab.c ++++ b/bfd/elf-strtab.c +@@ -215,16 +215,45 @@ _bfd_elf_strtab_clear_all_refs (struct elf_strtab_hash *tab) + tab->array[idx]->refcount = 0; + } + +-/* Downsizes strtab. Entries from IDX up to the current size are +- removed from the array. */ ++/* Save strtab refcounts prior to adding --as-needed library. */ ++ ++struct strtab_save ++{ ++ bfd_size_type size; ++ unsigned int refcount[1]; ++}; ++ ++void * ++_bfd_elf_strtab_save (struct elf_strtab_hash *tab) ++{ ++ struct strtab_save *save; ++ bfd_size_type idx, size; ++ ++ size = sizeof (*save) + (tab->size - 1) * sizeof (save->refcount[0]); ++ save = bfd_malloc (size); ++ if (save == NULL) ++ return save; ++ ++ save->size = tab->size; ++ for (idx = 1; idx < tab->size; idx++) ++ save->refcount[idx] = tab->array[idx]->refcount; ++ return save; ++} ++ ++/* Restore strtab refcounts on finding --as-needed library not needed. */ ++ + void +-_bfd_elf_strtab_restore_size (struct elf_strtab_hash *tab, bfd_size_type idx) ++_bfd_elf_strtab_restore (struct elf_strtab_hash *tab, void *buf) + { +- bfd_size_type curr_size = tab->size; ++ bfd_size_type idx, curr_size = tab->size; ++ struct strtab_save *save = (struct strtab_save *) buf; + + BFD_ASSERT (tab->sec_size == 0); +- BFD_ASSERT (idx <= curr_size); +- tab->size = idx; ++ BFD_ASSERT (save->size <= curr_size); ++ tab->size = save->size; ++ for (idx = 1; idx < save->size; ++idx) ++ tab->array[idx]->refcount = save->refcount[idx]; ++ + for (; idx < curr_size; ++idx) + { + /* We don't remove entries from the hash table, just set their +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index 5affc76..b585e5b 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -7374,18 +7374,21 @@ is_thumb2_vldm (const insn32 insn) + { + /* A6.5 Extension register load or store instruction + A7.7.229 +- We look only for the 32-bit registers case since the DP (64-bit +- registers) are not supported for STM32L4XX ++ We look for SP 32-bit and DP 64-bit registers. ++ Encoding T1 VLDM{mode} {!}, ++ is consecutive 64-bit registers ++ 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii + Encoding T2 VLDM{mode} {!}, + is consecutive 32-bit registers + 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii + if P==0 && U==1 && W==1 && Rn=1101 VPOP + if PUW=010 || PUW=011 || PUW=101 VLDM. */ + return +- ((insn & 0xfe100f00) == 0xec100a00) ++ (((insn & 0xfe100f00) == 0xec100b00) || ++ ((insn & 0xfe100f00) == 0xec100a00)) + && /* (IA without !). */ + (((((insn << 7) >> 28) & 0xd) == 0x4) +- /* (IA with !), includes VPOP (when reg number is SP). */ ++ /* (IA with !), includes VPOP (when reg number is SP). */ + || ((((insn << 7) >> 28) & 0xd) == 0x5) + /* (DB with !). */ + || ((((insn << 7) >> 28) & 0xd) == 0x9)); +@@ -7402,19 +7405,19 @@ static bfd_boolean + stm32l4xx_need_create_replacing_stub (const insn32 insn, + bfd_arm_stm32l4xx_fix stm32l4xx_fix) + { +- int nb_regs = 0; ++ int nb_words = 0; + + /* The field encoding the register list is the same for both LDMIA + and LDMDB encodings. */ + if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn)) +- nb_regs = popcount (insn & 0x0000ffff); ++ nb_words = popcount (insn & 0x0000ffff); + else if (is_thumb2_vldm (insn)) +- nb_regs = (insn & 0xff); ++ nb_words = (insn & 0xff); + + /* DEFAULT mode accounts for the real bug condition situation, + ALL mode inserts stubs for each LDM/VLDM instruction (testing). */ + return +- (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_regs > 8 : ++ (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 : + (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE; + } + +@@ -16242,30 +16245,31 @@ create_instruction_sub (int target_reg, int source_reg, int value) + } + + static inline bfd_vma +-create_instruction_vldmia (int base_reg, int wback, int num_regs, ++create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words, + int first_reg) + { + /* A8.8.332 VLDM (A8-922) +- VLMD{MODE} Rn{!}, {list} (Encoding T2). */ +- bfd_vma patched_inst = 0xec900a00 ++ VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */ ++ bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00) + | (/*W=*/wback << 21) + | (base_reg << 16) +- | (num_regs & 0x000000ff) +- | (((unsigned)first_reg>>1) & 0x0000000f) << 12 ++ | (num_words & 0x000000ff) ++ | (((unsigned)first_reg >> 1) & 0x0000000f) << 12 + | (first_reg & 0x00000001) << 22; + + return patched_inst; + } + + static inline bfd_vma +-create_instruction_vldmdb (int base_reg, int num_regs, int first_reg) ++create_instruction_vldmdb (int base_reg, int is_dp, int num_words, ++ int first_reg) + { + /* A8.8.332 VLDM (A8-922) +- VLMD{MODE} Rn!, {} (Encoding T2). */ +- bfd_vma patched_inst = 0xed300a00 ++ VLMD{MODE} Rn!, {} (Encoding T1 or T2). */ ++ bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00) + | (base_reg << 16) +- | (num_regs & 0x000000ff) +- | (((unsigned)first_reg>>1) & 0x0000000f) << 12 ++ | (num_words & 0x000000ff) ++ | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12 + | (first_reg & 0x00000001) << 22; + + return patched_inst; +@@ -16745,15 +16749,15 @@ stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab, + const bfd_byte *const initial_insn_addr, + bfd_byte *const base_stub_contents) + { +- int num_regs = ((unsigned int)initial_insn << 24) >> 24; ++ int num_words = ((unsigned int) initial_insn << 24) >> 24; + bfd_byte *current_stub_contents = base_stub_contents; + + BFD_ASSERT (is_thumb2_vldm (initial_insn)); + + /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with +- smaller than 8 registers load sequences that do not cause the ++ smaller than 8 words load sequences that do not cause the + hardware issue. */ +- if (num_regs <= 8) ++ if (num_words <= 8) + { + /* Untouched instruction. */ + current_stub_contents = +@@ -16768,28 +16772,30 @@ stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab, + } + else + { ++ bfd_boolean is_dp = /* DP encoding. */ ++ (initial_insn & 0xfe100f00) == 0xec100b00; + bfd_boolean is_ia_nobang = /* (IA without !). */ + (((initial_insn << 7) >> 28) & 0xd) == 0x4; + bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */ + (((initial_insn << 7) >> 28) & 0xd) == 0x5; + bfd_boolean is_db_bang = /* (DB with !). */ + (((initial_insn << 7) >> 28) & 0xd) == 0x9; +- int base_reg = ((unsigned int)initial_insn << 12) >> 28; ++ int base_reg = ((unsigned int) initial_insn << 12) >> 28; + /* d = UInt (Vd:D);. */ +- int first_reg = ((((unsigned int)initial_insn << 16) >> 28) << 1) ++ int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1) + | (((unsigned int)initial_insn << 9) >> 31); + +- /* Compute the number of 8-register chunks needed to split. */ +- int chunks = (num_regs%8) ? (num_regs/8 + 1) : (num_regs/8); ++ /* Compute the number of 8-words chunks needed to split. */ ++ int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8); + int chunk; + + /* The test coverage has been done assuming the following + hypothesis that exactly one of the previous is_ predicates is + true. */ +- BFD_ASSERT ((is_ia_nobang ^ is_ia_bang ^ is_db_bang) && +- !(is_ia_nobang & is_ia_bang & is_db_bang)); ++ BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang) ++ && !(is_ia_nobang & is_ia_bang & is_db_bang)); + +- /* We treat the cutting of the register in one pass for all ++ /* We treat the cutting of the words in one pass for all + cases, then we emit the adjustments: + + vldm rx, {...} +@@ -16802,29 +16808,34 @@ stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab, + + vldmd rx!, {...} + -> vldmb rx!, {8_words_or_less} for each needed 8_word. */ +- for (chunk = 0; chunkroot.type == bfd_link_hash_defweak || !h->def_regular)))) || (ELIMINATE_COPY_RELOCS +@@ -1961,7 +1962,7 @@ do_size: + return FALSE; + } + +- if ((r_type == R_386_GOT32 || r_type == R_386_GOT32X) ++ if (r_type == R_386_GOT32X + && (h == NULL || h->type != STT_GNU_IFUNC)) + sec->need_convert_load = 1; + } @@ -2490,12 +2491,14 @@ elf_i386_allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) } else @@ -865,7 +1252,76 @@ index 300839b..79f339e 100644 h->plt.offset = (bfd_vma) -1; h->needs_plt = 0; } -@@ -4016,10 +4019,12 @@ elf_i386_relocate_section (bfd *output_bfd, +@@ -2813,14 +2816,16 @@ elf_i386_convert_load (bfd *abfd, asection *sec, + unsigned int nop; + bfd_vma nop_offset; + +- if (r_type != R_386_GOT32 && r_type != R_386_GOT32X) ++ /* Don't convert R_386_GOT32 since we can't tell if it is applied ++ to "mov $foo@GOT, %reg" which isn't a load via GOT. */ ++ if (r_type != R_386_GOT32X) + continue; + + roff = irel->r_offset; + if (roff < 2) + continue; + +- /* Addend for R_386_GOT32 and R_386_GOT32X relocations must be 0. */ ++ /* Addend for R_386_GOT32X relocation must be 0. */ + addend = bfd_get_32 (abfd, contents + roff); + if (addend != 0) + continue; +@@ -2828,13 +2833,11 @@ elf_i386_convert_load (bfd *abfd, asection *sec, + modrm = bfd_get_8 (abfd, contents + roff - 1); + baseless = (modrm & 0xc7) == 0x5; + +- if (r_type == R_386_GOT32X +- && baseless ++ if (baseless + && bfd_link_pic (link_info)) + { + /* For PIC, disallow R_386_GOT32X without a base register +- since we don't know what the GOT base is. Allow +- R_386_GOT32 for existing object files. */ ++ since we don't know what the GOT base is. */ + const char *name; + + if (r_symndx < symtab_hdr->sh_info) +@@ -2862,12 +2865,6 @@ elf_i386_convert_load (bfd *abfd, asection *sec, + /* It is OK to convert mov to lea. */ + if (opcode != 0x8b) + { +- /* Only convert R_386_GOT32X relocation for call, jmp or +- one of adc, add, and, cmp, or, sbb, sub, test, xor +- instructions. */ +- if (r_type != R_386_GOT32X) +- continue; +- + /* It is OK to convert indirect branch to direct branch. It + is OK to convert adc, add, and, cmp, or, sbb, sub, test, + xor only when PIC is false. */ +@@ -2875,8 +2872,8 @@ elf_i386_convert_load (bfd *abfd, asection *sec, + continue; + } + +- /* Try to convert R_386_GOT32 and R_386_GOT32X. Get the symbol +- referred to by the reloc. */ ++ /* Try to convert R_386_GOT32X. Get the symbol referred to by ++ the reloc. */ + if (r_symndx < symtab_hdr->sh_info) + { + isym = bfd_sym_from_r_symndx (&htab->sym_cache, +@@ -2988,8 +2985,7 @@ convert_load: + { + /* Convert "mov foo@GOT(%reg1), %reg2" to + "lea foo@GOTOFF(%reg1), %reg2". */ +- if (r_type == R_386_GOT32X +- && (baseless || !bfd_link_pic (link_info))) ++ if (baseless || !bfd_link_pic (link_info)) + { + r_type = R_386_32; + /* For R_386_32, convert +@@ -4016,10 +4012,12 @@ elf_i386_relocate_section (bfd *output_bfd, /* It is relative to .got.plt section. */ if (h->got.offset != (bfd_vma) -1) @@ -880,7 +1336,7 @@ index 300839b..79f339e 100644 else /* Use GOTPLT entry. */ relocation = (h->plt.offset / plt_entry_size - 1 + 3) * 4; -@@ -4285,8 +4290,8 @@ r_386_got32: +@@ -4285,8 +4283,8 @@ r_386_got32: else if (h != NULL && h->dynindx != -1 && (r_type == R_386_PC32 @@ -891,7 +1347,7 @@ index 300839b..79f339e 100644 || !h->def_regular)) outrel.r_info = ELF32_R_INFO (h->dynindx, r_type); else -@@ -5355,19 +5360,23 @@ elf_i386_reloc_type_class (const struct bfd_link_info *info, +@@ -5355,19 +5353,23 @@ elf_i386_reloc_type_class (const struct bfd_link_info *info, bfd *abfd = info->output_bfd; const struct elf_backend_data *bed = get_elf_backend_data (abfd); struct elf_link_hash_table *htab = elf_hash_table (info); @@ -927,6 +1383,18 @@ index 300839b..79f339e 100644 switch (ELF32_R_TYPE (rela->r_info)) { +diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c +index ea03598..cfc6e57 100644 +--- a/bfd/elf32-ppc.c ++++ b/bfd/elf32-ppc.c +@@ -5166,6 +5166,7 @@ ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info) + tga->root.type = bfd_link_hash_indirect; + tga->root.u.i.link = &opt->root; + ppc_elf_copy_indirect_symbol (info, opt, tga); ++ opt->forced_local = 0; + if (opt->dynindx != -1) + { + /* Use __tls_get_addr_opt in dynamic relocations. */ diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c index 3b628b4..aa9cfd2 100644 --- a/bfd/elf64-hppa.c @@ -972,7 +1440,7 @@ index 3b628b4..aa9cfd2 100644 /* Relocate the given INSN. VALUE should be the actual value we want diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c -index 162862c..ffe23e6 100644 +index 162862c..d72b631 100644 --- a/bfd/elf64-ppc.c +++ b/bfd/elf64-ppc.c @@ -4344,14 +4344,20 @@ create_linkage_sections (bfd *dynobj, struct bfd_link_info *info) @@ -1084,8 +1552,24 @@ index 162862c..ffe23e6 100644 return TRUE; } +@@ -8224,6 +8228,7 @@ ppc64_elf_tls_setup (struct bfd_link_info *info) + tga_fd->root.type = bfd_link_hash_indirect; + tga_fd->root.u.i.link = &opt_fd->root; + ppc64_elf_copy_indirect_symbol (info, opt_fd, tga_fd); ++ opt_fd->forced_local = 0; + if (opt_fd->dynindx != -1) + { + /* Use __tls_get_addr_opt in dynamic relocations. */ +@@ -8240,6 +8245,7 @@ ppc64_elf_tls_setup (struct bfd_link_info *info) + tga->root.type = bfd_link_hash_indirect; + tga->root.u.i.link = &opt->root; + ppc64_elf_copy_indirect_symbol (info, opt, tga); ++ opt->forced_local = 0; + _bfd_elf_link_hash_hide_symbol (info, opt, + tga->forced_local); + htab->tls_get_addr = (struct ppc_link_hash_entry *) opt; diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c -index 63957bb..e80fd20 100644 +index 63957bb..7261405 100644 --- a/bfd/elf64-x86-64.c +++ b/bfd/elf64-x86-64.c @@ -2029,7 +2029,8 @@ do_size: @@ -1113,7 +1597,19 @@ index 63957bb..e80fd20 100644 h->plt.offset = (bfd_vma) -1; h->needs_plt = 0; } -@@ -3190,35 +3193,43 @@ elf_x86_64_convert_load (bfd *abfd, asection *sec, +@@ -3151,6 +3154,11 @@ elf_x86_64_convert_load (bfd *abfd, asection *sec, + continue; + } + ++ /* Don't convert GOTPCREL relocation against large section. */ ++ if (elf_section_data (tsec) != NULL ++ && (elf_section_flags (tsec) & SHF_X86_64_LARGE) != 0) ++ continue; ++ + if (tsec->sec_info_type == SEC_INFO_TYPE_MERGE) + { + /* At this stage in linking, no SEC_MERGE symbol has been +@@ -3190,35 +3198,46 @@ elf_x86_64_convert_load (bfd *abfd, asection *sec, } else { @@ -1137,24 +1633,29 @@ index 63957bb..e80fd20 100644 - for (i = asect->output_section->map_head.s; - i != NULL; - i = i->map_head.s) +- { +- size = align_power (size, i->alignment_power); +- size += i->size; +- } + asection *asect; + bfd_size_type size = 0; + for (asect = link_info->output_bfd->sections; + asect != NULL; + asect = asect->next) - { -- size = align_power (size, i->alignment_power); -- size += i->size; -+ asection *i; -+ for (i = asect->map_head.s; -+ i != NULL; -+ i = i->map_head.s) -+ { -+ size = align_power (size, i->alignment_power); -+ size += i->size; -+ } -+ asect->compressed_size = size; - } ++ /* Skip debug sections since compressed_size is used to ++ compress debug sections. */ ++ if ((asect->flags & SEC_DEBUGGING) == 0) ++ { ++ asection *i; ++ for (i = asect->map_head.s; ++ i != NULL; ++ i = i->map_head.s) ++ { ++ size = align_power (size, i->alignment_power); ++ size += i->size; ++ } ++ asect->compressed_size = size; ++ } } /* Don't convert GOTPCREL relocations if TSEC isn't placed @@ -1172,7 +1673,7 @@ index 63957bb..e80fd20 100644 > 0xffffffff) continue; } -@@ -4631,8 +4642,8 @@ direct: +@@ -4631,8 +4650,8 @@ direct: else if (h != NULL && h->dynindx != -1 && (IS_X86_64_PCREL_TYPE (r_type) @@ -1183,7 +1684,7 @@ index 63957bb..e80fd20 100644 || ! h->def_regular)) { outrel.r_info = htab->r_info (h->dynindx, r_type); -@@ -5728,19 +5739,23 @@ elf_x86_64_reloc_type_class (const struct bfd_link_info *info, +@@ -5728,19 +5747,23 @@ elf_x86_64_reloc_type_class (const struct bfd_link_info *info, bfd *abfd = info->output_bfd; const struct elf_backend_data *bed = get_elf_backend_data (abfd); struct elf_x86_64_link_hash_table *htab = elf_x86_64_hash_table (info); @@ -1220,7 +1721,7 @@ index 63957bb..e80fd20 100644 switch ((int) ELF32_R_TYPE (rela->r_info)) { diff --git a/bfd/elflink.c b/bfd/elflink.c -index 3d37bb4..842e85b 100644 +index 3d37bb4..4e7de0c 100644 --- a/bfd/elflink.c +++ b/bfd/elflink.c @@ -555,6 +555,19 @@ bfd_elf_record_link_assignment (bfd *output_bfd, @@ -1243,7 +1744,39 @@ index 3d37bb4..842e85b 100644 switch (h->root.type) { case bfd_link_hash_defined: -@@ -1472,13 +1485,16 @@ _bfd_elf_merge_symbol (bfd *abfd, +@@ -1171,21 +1184,20 @@ _bfd_elf_merge_symbol (bfd *abfd, + oldfunc = (h->type != STT_NOTYPE + && bed->is_function_type (h->type)); + +- /* When we try to create a default indirect symbol from the dynamic +- definition with the default version, we skip it if its type and +- the type of existing regular definition mismatch. */ ++ /* If creating a default indirect symbol ("foo" or "foo@") from a ++ dynamic versioned definition ("foo@@") skip doing so if there is ++ an existing regular definition with a different type. We don't ++ want, for example, a "time" variable in the executable overriding ++ a "time" function in a shared library. */ + if (pold_alignment == NULL + && newdyn + && newdef + && !olddyn +- && (((olddef || h->root.type == bfd_link_hash_common) +- && ELF_ST_TYPE (sym->st_info) != h->type +- && ELF_ST_TYPE (sym->st_info) != STT_NOTYPE +- && h->type != STT_NOTYPE +- && !(newfunc && oldfunc)) +- || (olddef +- && ((h->type == STT_GNU_IFUNC) +- != (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC))))) ++ && (olddef || h->root.type == bfd_link_hash_common) ++ && ELF_ST_TYPE (sym->st_info) != h->type ++ && ELF_ST_TYPE (sym->st_info) != STT_NOTYPE ++ && h->type != STT_NOTYPE ++ && !(newfunc && oldfunc)) + { + *skip = TRUE; + return TRUE; +@@ -1472,13 +1484,16 @@ _bfd_elf_merge_symbol (bfd *abfd, represent variables; this can cause confusion in principle, but any such confusion would seem to indicate an erroneous program or shared library. We also permit a common symbol in a regular @@ -1262,7 +1795,61 @@ index 3d37bb4..842e85b 100644 { *override = TRUE; newdef = FALSE; -@@ -4562,8 +4578,10 @@ error_free_dyn: +@@ -1750,6 +1765,31 @@ _bfd_elf_add_default_symbol (bfd *abfd, + if (skip) + goto nondefault; + ++ if (hi->def_regular) ++ { ++ /* If the undecorated symbol will have a version added by a ++ script different to H, then don't indirect to/from the ++ undecorated symbol. This isn't ideal because we may not yet ++ have seen symbol versions, if given by a script on the ++ command line rather than via --version-script. */ ++ if (hi->verinfo.vertree == NULL && info->version_info != NULL) ++ { ++ bfd_boolean hide; ++ ++ hi->verinfo.vertree ++ = bfd_find_version_for_sym (info->version_info, ++ hi->root.root.string, &hide); ++ if (hi->verinfo.vertree != NULL && hide) ++ { ++ (*bed->elf_backend_hide_symbol) (info, hi, TRUE); ++ goto nondefault; ++ } ++ } ++ if (hi->verinfo.vertree != NULL ++ && strcmp (p + 1 + (p[1] == '@'), hi->verinfo.vertree->name) != 0) ++ goto nondefault; ++ } ++ + if (! override) + { + /* Add the default symbol if not performing a relocatable link. */ +@@ -3481,8 +3521,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info) + void *old_ent; + struct bfd_link_hash_entry *old_undefs = NULL; + struct bfd_link_hash_entry *old_undefs_tail = NULL; +- long old_dynsymcount = 0; +- bfd_size_type old_dynstr_size = 0; ++ void *old_strtab = NULL; + size_t tabsize = 0; + asection *s; + bfd_boolean just_syms; +@@ -3923,8 +3962,9 @@ error_free_dyn: + old_table = htab->root.table.table; + old_size = htab->root.table.size; + old_count = htab->root.table.count; +- old_dynsymcount = htab->dynsymcount; +- old_dynstr_size = _bfd_elf_strtab_size (htab->dynstr); ++ old_strtab = _bfd_elf_strtab_save (htab->dynstr); ++ if (old_strtab == NULL) ++ goto error_free_vers; + + for (i = 0; i < htab->root.table.size; i++) + { +@@ -4562,8 +4602,10 @@ error_free_dyn: break; } @@ -1274,6 +1861,36 @@ index 3d37bb4..842e85b 100644 && definition && ((dynsym && h->ref_regular_nonweak +@@ -4633,7 +4675,9 @@ error_free_dyn: + memcpy (htab->root.table.table, old_tab, tabsize); + htab->root.undefs = old_undefs; + htab->root.undefs_tail = old_undefs_tail; +- _bfd_elf_strtab_restore_size (htab->dynstr, old_dynstr_size); ++ _bfd_elf_strtab_restore (htab->dynstr, old_strtab); ++ free (old_strtab); ++ old_strtab = NULL; + for (i = 0; i < htab->root.table.size; i++) + { + struct bfd_hash_entry *p; +@@ -4646,9 +4690,6 @@ error_free_dyn: + h = (struct elf_link_hash_entry *) p; + if (h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; +- if (h->dynindx >= old_dynsymcount +- && h->dynstr_index < old_dynstr_size) +- _bfd_elf_strtab_delref (htab->dynstr, h->dynstr_index); + + /* Preserve the maximum alignment and size for common + symbols even if this dynamic lib isn't on DT_NEEDED +@@ -5018,6 +5059,8 @@ error_free_dyn: + error_free_vers: + if (old_tab != NULL) + free (old_tab); ++ if (old_strtab != NULL) ++ free (old_strtab); + if (nondeflt_vers != NULL) + free (nondeflt_vers); + if (extversym != NULL) diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index 59c51cc..d83dc1b 100644 --- a/bfd/elfnn-aarch64.c @@ -1330,12 +1947,12 @@ index 59c51cc..d83dc1b 100644 value = _bfd_aarch64_elf_resolve_relocation (bfd_r_type, place, value, signed_addend, weak_undef_p); diff --git a/bfd/version.h b/bfd/version.h -index ed51cc9..3ee7efe 100644 +index ed51cc9..7d96419 100644 --- a/bfd/version.h +++ b/bfd/version.h @@ -1,4 +1,4 @@ -#define BFD_VERSION_DATE 20160125 -+#define BFD_VERSION_DATE 20160318 ++#define BFD_VERSION_DATE 20160613 #define BFD_VERSION @bfd_version@ #define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@ #define REPORT_BUGS_TO @report_bugs_to@ @@ -1347,10 +1964,14 @@ index 9fb81c5..607d328 100644 -m4_define([BFD_VERSION], [2.26]) +m4_define([BFD_VERSION], [2.26.0]) diff --git a/binutils/ChangeLog b/binutils/ChangeLog -index 2250b30..0a8dcd8 100644 +index 2250b30..81cb7bd 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog -@@ -1,3 +1,34 @@ +@@ -1,3 +1,38 @@ ++2016-06-13 Alan Modra ++ ++ * objcopy.c (copy_main): Init newsym->othersym. ++ +2016-03-14 H.J. Lu + + Backport from master @@ -1385,7 +2006,7 @@ index 2250b30..0a8dcd8 100644 2016-01-25 Tristan Gingold * configure: Regenerate. -@@ -238,12 +269,12 @@ +@@ -238,12 +273,12 @@ 2015-07-10 H.J. Lu @@ -1527,6 +2148,18 @@ index 7dc09c3..2e424ef 100644 @option{--compress-debug-sections=zlib} and @option{--compress-debug-sections=zlib-gabi} are equivalent to @option{--compress-debug-sections}. +diff --git a/binutils/objcopy.c b/binutils/objcopy.c +index 4a9f043..7feddb4 100644 +--- a/binutils/objcopy.c ++++ b/binutils/objcopy.c +@@ -4096,6 +4096,7 @@ copy_main (int argc, char *argv[]) + } + + t = strchr (t + 1, ','); ++ newsym->othersym = NULL; + if (t) + newsym->flags = parse_symflags (t+1, &newsym->othersym); + else diff --git a/binutils/testsuite/ChangeLog b/binutils/testsuite/ChangeLog index c579c69..52ddadc 100644 --- a/binutils/testsuite/ChangeLog @@ -1736,10 +2369,54 @@ index 0f54787..f95130a 100644 2009-10-09 Mikolaj Zalewski diff --git a/gas/ChangeLog b/gas/ChangeLog -index 534a954..96a8822 100644 +index 534a954..4ef4094 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog -@@ -1,3 +1,70 @@ +@@ -1,3 +1,114 @@ ++2016-06-03 Peter Bergner ++ ++ Backport from master ++ 2016-06-03 Peter Bergner ++ ++ PR binutils/20196 ++ * gas/testsuite/gas/ppc/e6500.s : Add tests. ++ * gas/testsuite/gas/ppc/e6500.d: Likewise. ++ * gas/testsuite/gas/ppc/power8.s: Likewise. ++ * gas/testsuite/gas/ppc/power8.d: Likewise. ++ * gas/testsuite/gas/ppc/power4.s : Add tests. ++ * gas/testsuite/gas/ppc/power4.d: Likewise. ++ ++2016-06-01 Peter Bergner ++ ++ Backport from master ++ 2016-05-26 Peter Bergner ++ ++ * testsuite/gas/ppc/altivec3.d : Add test. ++ * testsuite/gas/ppc/altivec3.s: Likewise. ++ * testsuite/gas/ppc/power9.d : Add tests. ++ * testsuite/gas/ppc/power9.s: Likewise. ++ ++2016-05-11 Nick Clifton ++ ++ PR gas/20047 ++ * config/tc-arc.c (md_parse_option): Return 1 for recognised dummy ++ options. ++ ++2016-04-15 H.J. Lu ++ ++ Backport from master ++ 2016-04-04 H.J. Lu ++ ++ PR gas/19909 ++ * config/tc-i386.c (check_VecOperands): Try vec_disp8 encoding ++ only if i.disp_encoding != disp_encoding_32bit. ++ * gas/testsuite/gas/i386/disp32.s: Add tests for vmovdqu64.d32. ++ * gas/testsuite/gas/i386/x86-64-disp32.s: Likewise. ++ * gas/testsuite/gas/i386/disp32.d: Updated. ++ * gas/testsuite/gas/i386/x86-64-disp32.d: Likewise. ++ +2016-02-20 H.J. Lu + + Backport from master @@ -1810,7 +2487,7 @@ index 534a954..96a8822 100644 2016-01-25 Tristan Gingold * configure: Regenerate. -@@ -8,12 +75,8 @@ +@@ -8,12 +119,8 @@ 2015-12-17 Ramana Radhakrishnan @@ -1824,7 +2501,7 @@ index 534a954..96a8822 100644 2015-12-15 Nick Clifton -@@ -320,10 +383,10 @@ +@@ -320,10 +427,10 @@ 2015-10-07 Claudiu Zissulescu @@ -1839,7 +2516,7 @@ index 534a954..96a8822 100644 2015-10-02 Renlin Li -@@ -572,9 +635,9 @@ +@@ -572,9 +679,9 @@ 2015-08-17 Alan Modra @@ -1851,7 +2528,7 @@ index 534a954..96a8822 100644 * read.c (s_align): Modify for TC_ALIGN_ZERO_IS_DEFAULT. 2015-08-13 Alan Modra -@@ -952,7 +1015,7 @@ +@@ -952,7 +1059,7 @@ 2015-06-11 John David Anglin PR gas/18427 @@ -1860,7 +2537,7 @@ index 534a954..96a8822 100644 (pa_get_label): Return last label in current space/segment or NULL. (pa_define_label): Record last label and add to root. (pa_undefine_label): Remove last label from root. -@@ -1028,7 +1091,6 @@ +@@ -1028,7 +1135,6 @@ Bernd Schmidt Paul Brook @@ -1868,7 +2545,7 @@ index 534a954..96a8822 100644 * config/tc-alpha.c (all_cfi_sections): Declare. (s_alpha_ent): Initialize all_cfi_sections. (alpha_elf_md_end): Invoke cfi_set_sections. -@@ -1796,7 +1858,7 @@ +@@ -1796,7 +1902,7 @@ 2015-01-12 Jan Beulich @@ -1877,7 +2554,7 @@ index 534a954..96a8822 100644 (cfi_pseudo_table): Add "cfi_label". (output_cfi_insn): Handle CFI_label. (select_cie_for_fde): Als terminate CIE when encountering -@@ -1809,7 +1871,7 @@ +@@ -1809,7 +1915,7 @@ 2015-01-12 Jan Beulich @@ -1926,8 +2603,20 @@ index 35c8202..8b040fc 100644 /* Supported emulations. */ #undef EMULATIONS +diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c +index ca43566..1ec01cb 100644 +--- a/gas/config/tc-arc.c ++++ b/gas/config/tc-arc.c +@@ -1747,6 +1747,7 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) + case OPTION_RTSC: + case OPTION_FPUDA: + /* Dummy options. */ ++ break; + + default: + return 0; diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c -index 1573043..8676c5f 100644 +index 1573043..664f381 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -552,6 +552,10 @@ static int allow_index_reg = 0; @@ -1951,7 +2640,18 @@ index 1573043..8676c5f 100644 return nr; } -@@ -7241,9 +7248,14 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off) +@@ -4557,7 +4564,9 @@ check_VecOperands (const insn_template *t) + && i.op[op].disps->X_op == O_constant) + { + offsetT value = i.op[op].disps->X_add_number; +- int vec_disp8_ok = fits_in_vec_disp8 (value); ++ int vec_disp8_ok ++ = (i.disp_encoding != disp_encoding_32bit ++ && fits_in_vec_disp8 (value)); + if (t->operand_types [op].bitfield.vec_disp8) + { + if (vec_disp8_ok) +@@ -7241,9 +7250,14 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off) /* Check for "call/jmp *mem", "mov mem, %reg", "test %reg, mem" and "binop mem, %reg" where binop is one of adc, add, and, cmp, or, sbb, sub, xor @@ -1969,7 +2669,7 @@ index 1573043..8676c5f 100644 && ((i.operands == 1 && i.tm.base_opcode == 0xff && (i.rm.reg == 2 || i.rm.reg == 4)) -@@ -9616,6 +9628,7 @@ const char *md_shortopts = "qn"; +@@ -9616,6 +9630,7 @@ const char *md_shortopts = "qn"; #define OPTION_MSHARED (OPTION_MD_BASE + 21) #define OPTION_MAMD64 (OPTION_MD_BASE + 22) #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) @@ -1977,7 +2677,7 @@ index 1573043..8676c5f 100644 struct option md_longopts[] = { -@@ -9647,6 +9660,7 @@ struct option md_longopts[] = +@@ -9647,6 +9662,7 @@ struct option md_longopts[] = {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, #endif {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX}, @@ -1985,7 +2685,7 @@ index 1573043..8676c5f 100644 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, {"mamd64", no_argument, NULL, OPTION_MAMD64}, {"mintel64", no_argument, NULL, OPTION_MINTEL64}, -@@ -9966,6 +9980,15 @@ md_parse_option (int c, char *arg) +@@ -9966,6 +9982,15 @@ md_parse_option (int c, char *arg) as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); break; @@ -2001,7 +2701,7 @@ index 1573043..8676c5f 100644 case OPTION_MAMD64: cpu_arch_flags.bitfield.cpuamd64 = 1; cpu_arch_flags.bitfield.cpuintel64 = 0; -@@ -10146,6 +10169,9 @@ md_show_usage (FILE *stream) +@@ -10146,6 +10171,9 @@ md_show_usage (FILE *stream) -momit-lock-prefix=[no|yes]\n\ strip all lock prefixes\n")); fprintf (stream, _("\ @@ -2324,6 +3024,52 @@ index 4c86c8c..2c01d7b 100644 * gas/mips/compact-eh-1.s: New file. * gas/mips/compact-eh-2.s: New file. * gas/mips/compact-eh-3.s: New file. +diff --git a/gas/testsuite/gas/i386/disp32.d b/gas/testsuite/gas/i386/disp32.d +index a3255fa..24ada81 100644 +--- a/gas/testsuite/gas/i386/disp32.d ++++ b/gas/testsuite/gas/i386/disp32.d +@@ -15,11 +15,12 @@ Disassembly of section .text: + [ ]*[a-f0-9]+: 8b 98 ff 0f 00 00 mov 0xfff\(%eax\),%ebx + [ ]*[a-f0-9]+: 8b 98 00 00 00 00 mov 0x0\(%eax\),%ebx + [ ]*[a-f0-9]+: 8b 98 03 00 00 00 mov 0x3\(%eax\),%ebx +-[ ]*[a-f0-9]+: eb 07 jmp 26 +-[ ]*[a-f0-9]+: eb 05 jmp 26 +-[ ]*[a-f0-9]+: e9 00 00 00 00 jmp 26 ++[ ]*[a-f0-9]+: 62 f1 fe 08 6f 98 c0 ff ff ff vmovdqu64 -0x40\(%eax\),%xmm3 ++[ ]*[a-f0-9]+: eb 07 jmp 30 ++[ ]*[a-f0-9]+: eb 05 jmp 30 ++[ ]*[a-f0-9]+: e9 00 00 00 00 jmp 30 + +-0+26 : ++0+30 : + [ ]*[a-f0-9]+: 89 18 mov %ebx,\(%eax\) + [ ]*[a-f0-9]+: 89 58 03 mov %ebx,0x3\(%eax\) + [ ]*[a-f0-9]+: 89 98 ff 0f 00 00 mov %ebx,0xfff\(%eax\) +@@ -27,4 +28,5 @@ Disassembly of section .text: + [ ]*[a-f0-9]+: 89 58 03 mov %ebx,0x3\(%eax\) + [ ]*[a-f0-9]+: 89 98 00 00 00 00 mov %ebx,0x0\(%eax\) + [ ]*[a-f0-9]+: 89 98 03 00 00 00 mov %ebx,0x3\(%eax\) ++[ ]*[a-f0-9]+: 62 f1 fe 08 6f 98 c0 ff ff ff vmovdqu64 -0x40\(%eax\),%xmm3 + #pass +diff --git a/gas/testsuite/gas/i386/disp32.s b/gas/testsuite/gas/i386/disp32.s +index c3bec3a..fa85ae5 100644 +--- a/gas/testsuite/gas/i386/disp32.s ++++ b/gas/testsuite/gas/i386/disp32.s +@@ -9,6 +9,8 @@ + mov.d32 (%eax),%ebx + mov.d32 3(%eax),%ebx + ++ vmovdqu64.d32 -0x40(%eax),%xmm3 ++ + jmp foo + jmp.d8 foo + jmp.d32 foo +@@ -24,3 +26,5 @@ foo: + + mov.d32 DWORD PTR [eax], ebx + mov.d32 DWORD PTR [eax+3], ebx ++ ++ vmovdqu64.d32 xmm3,XMMWORD PTR [eax-0x40] diff --git a/gas/testsuite/gas/i386/got-no-relax.d b/gas/testsuite/gas/i386/got-no-relax.d new file mode 100644 index 0000000..6bf138a @@ -2497,6 +3243,51 @@ index fa42326..e2cbb12 100644 vgatherqps ymm30{k1}, YMMWORD PTR [r14+zmm31*8-123] # AVX512F vgatherqps ymm30{k1}, YMMWORD PTR [r14+zmm31*8-123] # AVX512F +diff --git a/gas/testsuite/gas/i386/x86-64-disp32.d b/gas/testsuite/gas/i386/x86-64-disp32.d +index 8e307ee..da5dcb0 100644 +--- a/gas/testsuite/gas/i386/x86-64-disp32.d ++++ b/gas/testsuite/gas/i386/x86-64-disp32.d +@@ -15,11 +15,12 @@ Disassembly of section .text: + [ ]*[a-f0-9]+: 8b 98 ff 0f 00 00 mov 0xfff\(%rax\),%ebx + [ ]*[a-f0-9]+: 8b 98 00 00 00 00 mov 0x0\(%rax\),%ebx + [ ]*[a-f0-9]+: 8b 98 03 00 00 00 mov 0x3\(%rax\),%ebx +-[ ]*[a-f0-9]+: eb 07 jmp 26 +-[ ]*[a-f0-9]+: eb 05 jmp 26 +-[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 26 ++[ ]*[a-f0-9]+: 62 f1 fe 08 6f 98 c0 ff ff ff vmovdqu64 -0x40\(%rax\),%xmm3 ++[ ]*[a-f0-9]+: eb 07 jmp 30 ++[ ]*[a-f0-9]+: eb 05 jmp 30 ++[ ]*[a-f0-9]+: e9 00 00 00 00 jmpq 30 + +-0+26 : ++0+30 : + [ ]*[a-f0-9]+: 89 18 mov %ebx,\(%rax\) + [ ]*[a-f0-9]+: 89 58 03 mov %ebx,0x3\(%rax\) + [ ]*[a-f0-9]+: 89 98 ff 0f 00 00 mov %ebx,0xfff\(%rax\) +@@ -27,4 +28,5 @@ Disassembly of section .text: + [ ]*[a-f0-9]+: 89 58 03 mov %ebx,0x3\(%rax\) + [ ]*[a-f0-9]+: 89 98 00 00 00 00 mov %ebx,0x0\(%rax\) + [ ]*[a-f0-9]+: 89 98 03 00 00 00 mov %ebx,0x3\(%rax\) ++[ ]*[a-f0-9]+: 62 f1 fe 08 6f 98 c0 ff ff ff vmovdqu64 -0x40\(%rax\),%xmm3 + #pass +diff --git a/gas/testsuite/gas/i386/x86-64-disp32.s b/gas/testsuite/gas/i386/x86-64-disp32.s +index 0856339..e00aa02 100644 +--- a/gas/testsuite/gas/i386/x86-64-disp32.s ++++ b/gas/testsuite/gas/i386/x86-64-disp32.s +@@ -8,6 +8,7 @@ + + mov.d32 (%rax),%ebx + mov.d32 3(%rax),%ebx ++ vmovdqu64.d32 -0x40(%rax),%xmm3 + + jmp foo + jmp.d8 foo +@@ -24,3 +25,5 @@ foo: + + mov.d32 DWORD PTR [rax], ebx + mov.d32 DWORD PTR [rax+3], ebx ++ ++ vmovdqu64.d32 xmm3,XMMWORD PTR [rax-0x40] diff --git a/gas/testsuite/gas/i386/x86-64-gotpcrel-no-relax.d b/gas/testsuite/gas/i386/x86-64-gotpcrel-no-relax.d new file mode 100644 index 0000000..a3f8943 @@ -2548,11 +3339,266 @@ index 0a07149..bafaa9c 100644 #readelf: -rsW #name: x86-64 local PIC +diff --git a/gas/testsuite/gas/ppc/altivec3.d b/gas/testsuite/gas/ppc/altivec3.d +index 1d05a8f..7b7ae0b 100644 +--- a/gas/testsuite/gas/ppc/altivec3.d ++++ b/gas/testsuite/gas/ppc/altivec3.d +@@ -76,4 +76,5 @@ Disassembly of section \.text: + .*: (12 b5 17 44|44 17 b5 12) vslv v21,v21,v2 + .*: (11 e9 0f 4d|4d 0f e9 11) vextuhrx r15,r9,v1 + .*: (12 b1 87 8d|8d 87 b1 12) vextuwrx r21,r17,v16 ++.*: (12 95 b5 e3|e3 b5 95 12) vmsumudm v20,v21,v22,v23 + #pass +diff --git a/gas/testsuite/gas/ppc/altivec3.s b/gas/testsuite/gas/ppc/altivec3.s +index 6217da5..7fa28b3 100644 +--- a/gas/testsuite/gas/ppc/altivec3.s ++++ b/gas/testsuite/gas/ppc/altivec3.s +@@ -67,3 +67,4 @@ start: + vslv 21,21,2 + vextuhrx 15,9,1 + vextuwrx 21,17,16 ++ vmsumudm 20,21,22,23 +diff --git a/gas/testsuite/gas/ppc/e6500.d b/gas/testsuite/gas/ppc/e6500.d +index c8d8f57..3ed94dc 100644 +--- a/gas/testsuite/gas/ppc/e6500.d ++++ b/gas/testsuite/gas/ppc/e6500.d +@@ -73,3 +73,20 @@ Disassembly of section \.text: + fc: (7c 43 09 8d|8d 09 43 7c) icblq. 2,r3,r1 + 100: (7c 10 02 dc|dc 02 10 7c) mftmr r0,16 + 104: (7c 10 03 dc|dc 03 10 7c) mttmr 16,r0 ++.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7 ++.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7 ++.*: (7e a0 40 e8|e8 40 a0 7e) lharx r21,0,r8 ++.*: (7e a1 40 e8|e8 40 a1 7e) lharx r21,r1,r8 ++.*: (7e c0 48 28|28 48 c0 7e) lwarx r22,0,r9 ++.*: (7e c1 48 28|28 48 c1 7e) lwarx r22,r1,r9 ++.*: (7e e0 50 a8|a8 50 e0 7e) ldarx r23,0,r10 ++.*: (7e e1 50 a8|a8 50 e1 7e) ldarx r23,r1,r10 ++.*: (7d 40 3d 6d|6d 3d 40 7d) stbcx\. r10,0,r7 ++.*: (7d 41 3d 6d|6d 3d 41 7d) stbcx\. r10,r1,r7 ++.*: (7d 60 45 ad|ad 45 60 7d) sthcx\. r11,0,r8 ++.*: (7d 61 45 ad|ad 45 61 7d) sthcx\. r11,r1,r8 ++.*: (7d 80 49 2d|2d 49 80 7d) stwcx\. r12,0,r9 ++.*: (7d 81 49 2d|2d 49 81 7d) stwcx\. r12,r1,r9 ++.*: (7d a0 51 ad|ad 51 a0 7d) stdcx\. r13,0,r10 ++.*: (7d a1 51 ad|ad 51 a1 7d) stdcx\. r13,r1,r10 ++#pass +diff --git a/gas/testsuite/gas/ppc/e6500.s b/gas/testsuite/gas/ppc/e6500.s +index 2167cc6..d4b7f84 100644 +--- a/gas/testsuite/gas/ppc/e6500.s ++++ b/gas/testsuite/gas/ppc/e6500.s +@@ -67,3 +67,19 @@ start: + icblq. 2,3,1 + mftmr 0,16 + mttmr 16,0 ++ lbarx 20,0,7 ++ lbarx 20,1,7 ++ lharx 21,0,8 ++ lharx 21,1,8 ++ lwarx 22,0,9 ++ lwarx 22,1,9 ++ ldarx 23,0,10 ++ ldarx 23,1,10 ++ stbcx. 10,0,7 ++ stbcx. 10,1,7 ++ sthcx. 11,0,8 ++ sthcx. 11,1,8 ++ stwcx. 12,0,9 ++ stwcx. 12,1,9 ++ stdcx. 13,0,10 ++ stdcx. 13,1,10 +diff --git a/gas/testsuite/gas/ppc/power4.d b/gas/testsuite/gas/ppc/power4.d +index 8a09c05..cb487a7 100644 +--- a/gas/testsuite/gas/ppc/power4.d ++++ b/gas/testsuite/gas/ppc/power4.d +@@ -10,7 +10,7 @@ start address 0x0+ + + Sections: + Idx Name +Size +VMA +LMA +File off +Algn +- +0 \.text +0+e8 +0+ +0+ +.* ++ +0 \.text +0+108 +0+ +0+ +.* + +CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + +1 \.data +0+20 +0+ +0+ +.* + +CONTENTS, ALLOC, LOAD, DATA +@@ -106,3 +106,12 @@ Disassembly of section \.text: + .*: (7c 20 04 ac|ac 04 20 7c) lwsync + .*: (7c 40 04 ac|ac 04 40 7c) ptesync + .*: (7c 40 04 ac|ac 04 40 7c) ptesync ++.*: (7e 80 30 28|28 30 80 7e) lwarx r20,0,r6 ++.*: (7e 81 30 28|28 30 81 7e) lwarx r20,r1,r6 ++.*: (7e a0 38 a8|a8 38 a0 7e) ldarx r21,0,r7 ++.*: (7e a1 38 a8|a8 38 a1 7e) ldarx r21,r1,r7 ++.*: (7e c0 41 2d|2d 41 c0 7e) stwcx\. r22,0,r8 ++.*: (7e c1 41 2d|2d 41 c1 7e) stwcx\. r22,r1,r8 ++.*: (7e e0 49 ad|ad 49 e0 7e) stdcx\. r23,0,r9 ++.*: (7e e1 49 ad|ad 49 e1 7e) stdcx\. r23,r1,r9 ++#pass +diff --git a/gas/testsuite/gas/ppc/power4.s b/gas/testsuite/gas/ppc/power4.s +index 583284c..b2ede93 100644 +--- a/gas/testsuite/gas/ppc/power4.s ++++ b/gas/testsuite/gas/ppc/power4.s +@@ -79,6 +79,14 @@ dsym1: + sync 1 + ptesync + sync 2 ++ lwarx 20,0,6 ++ lwarx 20,1,6 ++ ldarx 21,0,7 ++ ldarx 21,1,7 ++ stwcx. 22,0,8 ++ stwcx. 22,1,8 ++ stdcx. 23,0,9 ++ stdcx. 23,1,9 + + .section ".data" + usym0: .llong 0xcafebabe +diff --git a/gas/testsuite/gas/ppc/power8.d b/gas/testsuite/gas/ppc/power8.d +index aaa64c8..5c97ab9 100644 +--- a/gas/testsuite/gas/ppc/power8.d ++++ b/gas/testsuite/gas/ppc/power8.d +@@ -160,4 +160,36 @@ Disassembly of section \.text: + .*: (7d 20 3f 99|99 3f 20 7d) stxvd2x vs41,0,r7 + .*: (7d 75 47 98|98 47 75 7d) stxvd2x vs11,r21,r8 + .*: (7d 75 47 98|98 47 75 7d) stxvd2x vs11,r21,r8 ++.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7 ++.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7 ++.*: (7e 80 38 69|69 38 80 7e) lbarx r20,0,r7,1 ++.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7 ++.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7 ++.*: (7e 81 38 69|69 38 81 7e) lbarx r20,r1,r7,1 ++.*: (7e a0 40 a8|a8 40 a0 7e) ldarx r21,0,r8 ++.*: (7e a0 40 a8|a8 40 a0 7e) ldarx r21,0,r8 ++.*: (7e a0 40 a9|a9 40 a0 7e) ldarx r21,0,r8,1 ++.*: (7e a1 40 a8|a8 40 a1 7e) ldarx r21,r1,r8 ++.*: (7e a1 40 a8|a8 40 a1 7e) ldarx r21,r1,r8 ++.*: (7e a1 40 a9|a9 40 a1 7e) ldarx r21,r1,r8,1 ++.*: (7e c0 48 e8|e8 48 c0 7e) lharx r22,0,r9 ++.*: (7e c0 48 e8|e8 48 c0 7e) lharx r22,0,r9 ++.*: (7e c0 48 e9|e9 48 c0 7e) lharx r22,0,r9,1 ++.*: (7e c1 48 e8|e8 48 c1 7e) lharx r22,r1,r9 ++.*: (7e c1 48 e8|e8 48 c1 7e) lharx r22,r1,r9 ++.*: (7e c1 48 e9|e9 48 c1 7e) lharx r22,r1,r9,1 ++.*: (7e e0 50 28|28 50 e0 7e) lwarx r23,0,r10 ++.*: (7e e0 50 28|28 50 e0 7e) lwarx r23,0,r10 ++.*: (7e e0 50 29|29 50 e0 7e) lwarx r23,0,r10,1 ++.*: (7e e1 50 28|28 50 e1 7e) lwarx r23,r1,r10 ++.*: (7e e1 50 28|28 50 e1 7e) lwarx r23,r1,r10 ++.*: (7e e1 50 29|29 50 e1 7e) lwarx r23,r1,r10,1 ++.*: (7d 40 3d 6d|6d 3d 40 7d) stbcx\. r10,0,r7 ++.*: (7d 41 3d 6d|6d 3d 41 7d) stbcx\. r10,r1,r7 ++.*: (7d 60 45 ad|ad 45 60 7d) sthcx\. r11,0,r8 ++.*: (7d 61 45 ad|ad 45 61 7d) sthcx\. r11,r1,r8 ++.*: (7d 80 49 2d|2d 49 80 7d) stwcx\. r12,0,r9 ++.*: (7d 81 49 2d|2d 49 81 7d) stwcx\. r12,r1,r9 ++.*: (7d a0 51 ad|ad 51 a0 7d) stdcx\. r13,0,r10 ++.*: (7d a1 51 ad|ad 51 a1 7d) stdcx\. r13,r1,r10 + #pass +diff --git a/gas/testsuite/gas/ppc/power8.s b/gas/testsuite/gas/ppc/power8.s +index 0b350eb..728caae 100644 +--- a/gas/testsuite/gas/ppc/power8.s ++++ b/gas/testsuite/gas/ppc/power8.s +@@ -152,3 +152,35 @@ power8: + stxvd2x 41,0,7 + stxvx 11,21,8 + stxvd2x 11,21,8 ++ lbarx 20,0,7 ++ lbarx 20,0,7,0 ++ lbarx 20,0,7,1 ++ lbarx 20,1,7 ++ lbarx 20,1,7,0 ++ lbarx 20,1,7,1 ++ ldarx 21,0,8 ++ ldarx 21,0,8,0 ++ ldarx 21,0,8,1 ++ ldarx 21,1,8 ++ ldarx 21,1,8,0 ++ ldarx 21,1,8,1 ++ lharx 22,0,9 ++ lharx 22,0,9,0 ++ lharx 22,0,9,1 ++ lharx 22,1,9 ++ lharx 22,1,9,0 ++ lharx 22,1,9,1 ++ lwarx 23,0,10 ++ lwarx 23,0,10,0 ++ lwarx 23,0,10,1 ++ lwarx 23,1,10 ++ lwarx 23,1,10,0 ++ lwarx 23,1,10,1 ++ stbcx. 10,0,7 ++ stbcx. 10,1,7 ++ sthcx. 11,0,8 ++ sthcx. 11,1,8 ++ stwcx. 12,0,9 ++ stwcx. 12,1,9 ++ stdcx. 13,0,10 ++ stdcx. 13,1,10 +diff --git a/gas/testsuite/gas/ppc/power9.d b/gas/testsuite/gas/ppc/power9.d +index 2e5593d..bbbf555 100644 +--- a/gas/testsuite/gas/ppc/power9.d ++++ b/gas/testsuite/gas/ppc/power9.d +@@ -363,6 +363,8 @@ Disassembly of section \.text: + .*: (7c 00 f6 e4|e4 f6 00 7c) rmieg r30 + .*: (7d 40 7a 6a|6a 7a 40 7d) ldmx r10,0,r15 + .*: (7d 43 7a 6a|6a 7a 43 7d) ldmx r10,r3,r15 ++.*: (7d 60 83 6a|6a 83 60 7d) lwzmx r11,0,r16 ++.*: (7d 63 83 6a|6a 83 63 7d) lwzmx r11,r3,r16 + .*: (4c 00 02 e4|e4 02 00 4c) stop + .*: (7c 00 00 3c|3c 00 00 7c) wait + .*: (7c 00 00 3c|3c 00 00 7c) wait +@@ -381,4 +383,11 @@ Disassembly of section \.text: + .*: (f0 6d bc 07|07 bc 6d f0) xsmaxcdp vs35,vs45,vs55 + .*: (f0 8e c4 c7|c7 c4 8e f0) xsminjdp vs36,vs46,vs56 + .*: (f0 af cc 87|87 cc af f0) xsmaxjdp vs37,vs47,vs57 ++.*: (12 95 b5 e3|e3 b5 95 12) vmsumudm v20,v21,v22,v23 ++.*: (7d 6c 69 54|54 69 6c 7d) addex r11,r12,r13,0 ++.*: (7d 6c 6b 54|54 6b 6c 7d) addex r11,r12,r13,1 ++.*: (7d 6c 6d 54|54 6d 6c 7d) addex r11,r12,r13,2 ++.*: (7e b6 b9 55|55 b9 b6 7e) addex\. r21,r22,r23,0 ++.*: (7e b6 bb 55|55 bb b6 7e) addex\. r21,r22,r23,1 ++.*: (7e b6 bd 55|55 bd b6 7e) addex\. r21,r22,r23,2 + #pass +diff --git a/gas/testsuite/gas/ppc/power9.s b/gas/testsuite/gas/ppc/power9.s +index 6ee49d4..16929a7 100644 +--- a/gas/testsuite/gas/ppc/power9.s ++++ b/gas/testsuite/gas/ppc/power9.s +@@ -354,6 +354,8 @@ power9: + rmieg 30 + ldmx 10,0,15 + ldmx 10,3,15 ++ lwzmx 11,0,16 ++ lwzmx 11,3,16 + stop + wait + wait 0 +@@ -372,3 +374,10 @@ power9: + xsmaxcdp 35,45,55 + xsminjdp 36,46,56 + xsmaxjdp 37,47,57 ++ vmsumudm 20,21,22,23 ++ addex 11,12,13,0 ++ addex 11,12,13,1 ++ addex 11,12,13,2 ++ addex. 21,22,23,0 ++ addex. 21,22,23,1 ++ addex. 21,22,23,2 diff --git a/gold/ChangeLog b/gold/ChangeLog -index b283a88..92b26ba 100644 +index b283a88..ec8dacb 100644 --- a/gold/ChangeLog +++ b/gold/ChangeLog -@@ -33,7 +33,7 @@ +@@ -1,3 +1,11 @@ ++2016-02-05 Sriraman Tallam ++ ++ PR gold/19047 ++ * icf.cc (get_rel_addend): New function. ++ (get_section_contents): Move merge section addend computation to a ++ new function. Ignore negative values for SHT_REL and SHT_RELA addends. ++ Fix bug to not read past the length of the section. ++ + 2015-12-16 Roland McGrath + + PR ld/17473 +@@ -33,7 +41,7 @@ 2015-11-11 Alan Modra Peter Bergner @@ -2561,7 +3607,7 @@ index b283a88..92b26ba 100644 (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. -@@ -339,7 +339,7 @@ +@@ -339,7 +347,7 @@ 2015-07-26 Doug Kwan * testsuite/arm_unaligned_reloc.{s,sh}: Make test less sensitive to @@ -2570,7 +3616,7 @@ index b283a88..92b26ba 100644 2015-07-23 Ian Coolidge Plumb --pic-veneer option for gold. -@@ -566,7 +566,7 @@ +@@ -566,7 +574,7 @@ 2015-06-29 Doug Kwan * testsuite/arm_bl_out_of_range.s: Align stub table so that it appears @@ -2579,7 +3625,7 @@ index b283a88..92b26ba 100644 * testsuite/arm_cortex_a8_b.s: Ditto. * testsuite/arm_cortex_a8_b_cond.s: Ditto. * testsuite/arm_cortex_a8_bl.s: Ditto. -@@ -940,7 +940,6 @@ +@@ -940,7 +948,6 @@ 2015-04-07 HC Yen Add AArch32 support for gold linker. @@ -2587,7 +3633,7 @@ index b283a88..92b26ba 100644 * arm.cc: Add V8 arch combine table. 2015-04-06 Rafael Ávila de Espíndola -@@ -1455,7 +1454,6 @@ +@@ -1455,7 +1462,6 @@ (Output_data_plt_arm::entry_count): Modified. (Output_data_plt_arm::address_for_global): New method. (Output_data_plt_arm::address_for_local): New method. @@ -2595,7 +3641,7 @@ index b283a88..92b26ba 100644 (Output_data_plt_arm::set_final_data_size): Add irelative_count_. (Output_data_plt_arm::insert_irelative_data): New method. (Output_data_plt_arm::irelative_rel_): New member. -@@ -2490,7 +2488,7 @@ gold/ +@@ -2490,7 +2496,7 @@ gold/ Add .gdb_index version 7 support. @@ -2604,7 +3650,7 @@ index b283a88..92b26ba 100644 (Dwarf_abbrev_table::do_read_abbrevs): Check for compressed debug sections. (Dwarf_ranges_table::read_ranges_table): Likewise. -@@ -2501,21 +2499,21 @@ gold/ +@@ -2501,21 +2507,21 @@ gold/ for end of list by offset, not by offset == 0. (Dwarf_info_reader::do_read_string_table): Check for compressed debug sections. @@ -2631,7 +3677,7 @@ index b283a88..92b26ba 100644 2014-01-08 H.J. Lu -@@ -5554,15 +5552,15 @@ gold/ +@@ -5554,15 +5560,15 @@ gold/ 2012-01-03 Cary Coutant @@ -2651,7 +3697,7 @@ index b283a88..92b26ba 100644 2011-12-18 Ian Lance Taylor -@@ -6073,10 +6071,10 @@ gold/ +@@ -6073,10 +6079,10 @@ gold/ 2011-08-01 Cary Coutant @@ -2666,7 +3712,7 @@ index b283a88..92b26ba 100644 2011-08-01 Cary Coutant -@@ -6402,7 +6400,7 @@ gold/ +@@ -6402,7 +6408,7 @@ gold/ 2011-07-06 Cary Coutant @@ -2675,7 +3721,7 @@ index b283a88..92b26ba 100644 (Output_section_incremental_inputs::write_info_blocks): Check for hidden and internal symbols. -@@ -6943,9 +6941,9 @@ gold/ +@@ -6943,9 +6949,9 @@ gold/ 2011-06-09 Cary Coutant PR gold/12804 @@ -2687,7 +3733,7 @@ index b283a88..92b26ba 100644 uncompressed size of compressed input sections. 2011-06-08 Cary Coutant -@@ -7073,10 +7071,10 @@ gold/ +@@ -7073,10 +7079,10 @@ gold/ 2011-06-02 Cary Coutant PR gold/12163 @@ -2700,7 +3746,7 @@ index b283a88..92b26ba 100644 2011-06-02 Nick Clifton -@@ -7593,9 +7591,9 @@ gold/ +@@ -7593,9 +7599,9 @@ gold/ 2011-04-14 Cary Coutant @@ -2713,7 +3759,7 @@ index b283a88..92b26ba 100644 2011-04-12 Ian Lance Taylor -@@ -8706,7 +8704,7 @@ gold/ +@@ -8706,7 +8712,7 @@ gold/ 2010-10-17 Doug Kwan @@ -2722,7 +3768,7 @@ index b283a88..92b26ba 100644 GOT output section to be writable. 2010-10-14 Cary Coutant -@@ -8858,7 +8856,7 @@ gold/ +@@ -8858,7 +8864,7 @@ gold/ 2010-09-30 Doug Kwan @@ -2731,7 +3777,7 @@ index b283a88..92b26ba 100644 2010-09-28 Sriraman Tallam -@@ -8902,13 +8900,13 @@ gold/ +@@ -8902,13 +8908,13 @@ gold/ 2010-09-15 Doug Kwan @@ -2752,7 +3798,7 @@ index b283a88..92b26ba 100644 2010-09-14 Cary Coutant -@@ -9041,7 +9039,7 @@ gold/ +@@ -9041,7 +9047,7 @@ gold/ 2010-08-27 Doug Kwan @@ -2761,7 +3807,7 @@ index b283a88..92b26ba 100644 reference override an existing dynamic weak reference. * testsuite/Makefile.am: Add new test dyn_weak_ref. * testsuite/Makefile.in: Regenerate. -@@ -9133,11 +9131,11 @@ gold/ +@@ -9133,11 +9139,11 @@ gold/ 2010-08-19 Neil Vachharajani Cary Coutant @@ -2776,7 +3822,7 @@ index b283a88..92b26ba 100644 this->this_blocker_ to Add_lib_group_symbols::set_blocker. * testsuite/Makefile.am (start_lib_test): New test case. * testsuite/Makefile.in: Regenerate. -@@ -9740,9 +9738,9 @@ gold/ +@@ -9740,9 +9746,9 @@ gold/ 2010-07-27 Jeffrey Yasskin * testsuite/debug_msg.sh: Test mixed weak/strong symbol behavior. @@ -2789,7 +3835,7 @@ index b283a88..92b26ba 100644 2010-07-21 Cary Coutant -@@ -10087,13 +10085,13 @@ gold/ +@@ -10087,13 +10093,13 @@ gold/ 2010-05-26 Rafael Espindola PR 11604 @@ -2809,7 +3855,7 @@ index b283a88..92b26ba 100644 2010-05-26 Rafael Espindola -@@ -10577,7 +10575,7 @@ gold/ +@@ -10577,7 +10583,7 @@ gold/ 2010-03-25 Doug Kwan @@ -2818,7 +3864,7 @@ index b283a88..92b26ba 100644 to avoid a conversion warning on a 32-bit host. 2010-03-24 Ian Lance Taylor -@@ -10781,7 +10779,7 @@ gold/ +@@ -10781,7 +10787,7 @@ gold/ 2010-03-08 Doug Kwan @@ -2827,7 +3873,7 @@ index b283a88..92b26ba 100644 due to a conversion warning. (Arm_relobj::update_output_local_symbol_count): Check for local symbol with unset output index. -@@ -11403,7 +11401,7 @@ gold/ +@@ -11403,7 +11409,7 @@ gold/ 2010-01-29 Viktor Kutuzov @@ -2836,7 +3882,7 @@ index b283a88..92b26ba 100644 R_ARM_THM_PC12, R_ARM_THM_ALU_PREL_11_0. (Arm_relocate_functions::thm_alu11): New Method. (Arm_relocate_functions::thm_pc8): New Method. -@@ -11553,12 +11551,12 @@ gold/ +@@ -11553,12 +11559,12 @@ gold/ 2010-01-22 Viktor Kutuzov @@ -2852,7 +3898,7 @@ index b283a88..92b26ba 100644 (General_options::parse_fix_v4bx_interworking): New method. 2010-01-22 Doug Kwan -@@ -11618,7 +11616,7 @@ gold/ +@@ -11618,7 +11624,7 @@ gold/ 2010-01-20 Viktor Kutuzov @@ -2861,7 +3907,7 @@ index b283a88..92b26ba 100644 (class Arm_v4bx_stub): New class. (DEF_STUBS): Updated definition to support v4_veneer_bx. (Stub_factory::make_arm_v4bx_stub): New method. -@@ -12675,7 +12673,7 @@ gold/ +@@ -12675,7 +12681,7 @@ gold/ attributes_section and attributes_vendor. * i386.cc (Target_i386::i386_info): Same. * object.cc (Sized_relobj::do_layout): Skip attribute section. @@ -2870,7 +3916,7 @@ index b283a88..92b26ba 100644 fields attributes_section and attributes_vendor. * sparc.cc (Target_sparc::sparc_info): Same. * target.h (Target::attributes_section, Target::attributes_vendor, -@@ -13322,7 +13320,7 @@ gold/ +@@ -13322,7 +13328,7 @@ gold/ (Segment_start_expression::value): New method definition. (script_exp_function_segment_start): Return a new Segment_start_expression. @@ -2879,7 +3925,7 @@ index b283a88..92b26ba 100644 prototype. * script-sections.cc (Script_sections::Script_sections): Initialize SAW_SEGMENT_START_EXPRESSION_ to false. -@@ -14113,9 +14111,9 @@ gold/ +@@ -14113,9 +14119,9 @@ gold/ (Script_sections::attach_sections_using_phdrs_clause): Do not modify segment list. (Script_sections::release_segments): New method definition. @@ -2891,7 +3937,7 @@ index b283a88..92b26ba 100644 Target::do_may_relax, Target::do_relax): New method definitions. 2009-09-17 Viktor Kutuzov -@@ -14689,7 +14687,7 @@ gold/ +@@ -14689,7 +14695,7 @@ gold/ 2009-06-03 Doug Kwan @@ -2900,7 +3946,7 @@ index b283a88..92b26ba 100644 (Target_arm::reloc_is_non_pic): Define new method. (class Arm_relocate_functions): New. (Target_arm::Relocate::relocate): Handle relocation types used by -@@ -14701,7 +14699,7 @@ gold/ +@@ -14701,7 +14707,7 @@ gold/ 2009-06-02 Doug Kwan @@ -2909,7 +3955,7 @@ index b283a88..92b26ba 100644 issued_non_pic_error_. (class Target_arm::Scan): Declare new method check_non_pic. Define new method symbol_needs_plt_entry. -@@ -14722,7 +14720,7 @@ gold/ +@@ -14722,7 +14728,7 @@ gold/ 2009-05-29 Doug Kwan @@ -2918,6 +3964,155 @@ index b283a88..92b26ba 100644 template class. (class Target_arm): Update comment. (Target_arm::Target_arm): Initialize new data members GOT_, +diff --git a/gold/icf.cc b/gold/icf.cc +index 96b7f2d..663d579 100644 +--- a/gold/icf.cc ++++ b/gold/icf.cc +@@ -213,6 +213,45 @@ preprocess_for_unique_sections(const std::vector& id_section, + } + } + ++// For SHF_MERGE sections that use REL relocations, the addend is stored in ++// the text section at the relocation offset. Read the addend value given ++// the pointer to the addend in the text section and the addend size. ++// Update the addend value if a valid addend is found. ++// Parameters: ++// RELOC_ADDEND_PTR : Pointer to the addend in the text section. ++// ADDEND_SIZE : The size of the addend. ++// RELOC_ADDEND_VALUE : Pointer to the addend that is updated. ++ ++inline void ++get_rel_addend(const unsigned char* reloc_addend_ptr, ++ const unsigned int addend_size, ++ uint64_t* reloc_addend_value) ++{ ++ switch (addend_size) ++ { ++ case 0: ++ break; ++ case 1: ++ *reloc_addend_value = ++ read_from_pointer<8>(reloc_addend_ptr); ++ break; ++ case 2: ++ *reloc_addend_value = ++ read_from_pointer<16>(reloc_addend_ptr); ++ break; ++ case 4: ++ *reloc_addend_value = ++ read_from_pointer<32>(reloc_addend_ptr); ++ break; ++ case 8: ++ *reloc_addend_value = ++ read_from_pointer<64>(reloc_addend_ptr); ++ break; ++ default: ++ gold_unreachable(); ++ } ++} ++ + // This returns the buffer containing the section's contents, both + // text and relocs. Relocs are differentiated as those pointing to + // sections that could be folded and those that cannot. Only relocs +@@ -397,58 +436,36 @@ get_section_contents(bool first_iteration, + uint64_t entsize = + (it_v->first)->section_entsize(it_v->second); + long long offset = it_a->first; +- +- unsigned long long addend = it_a->second; +- // Ignoring the addend when it is a negative value. See the +- // comments in Merged_symbol_value::Value in object.h. +- if (addend < 0xffffff00) +- offset = offset + addend; +- +- // For SHT_REL relocation sections, the addend is stored in the +- // text section at the relocation offset. +- uint64_t reloc_addend_value = 0; ++ // Handle SHT_RELA and SHT_REL addends, only one of these ++ // addends exists. ++ // Get the SHT_RELA addend. For RELA relocations, we have ++ // the addend from the relocation. ++ uint64_t reloc_addend_value = it_a->second; ++ ++ // Handle SHT_REL addends. ++ // For REL relocations, we need to fetch the addend from the ++ // section contents. + const unsigned char* reloc_addend_ptr = + contents + static_cast(*it_o); +- switch(*it_addend_size) +- { +- case 0: +- { +- break; +- } +- case 1: +- { +- reloc_addend_value = +- read_from_pointer<8>(reloc_addend_ptr); +- break; +- } +- case 2: +- { +- reloc_addend_value = +- read_from_pointer<16>(reloc_addend_ptr); +- break; +- } +- case 4: +- { +- reloc_addend_value = +- read_from_pointer<32>(reloc_addend_ptr); +- break; +- } +- case 8: +- { +- reloc_addend_value = +- read_from_pointer<64>(reloc_addend_ptr); +- break; +- } +- default: +- gold_unreachable(); +- } +- offset = offset + reloc_addend_value; ++ ++ // Update the addend value with the SHT_REL addend if ++ // available. ++ get_rel_addend(reloc_addend_ptr, *it_addend_size, ++ &reloc_addend_value); ++ ++ // Ignore the addend when it is a negative value. See the ++ // comments in Merged_symbol_value::value in object.h. ++ if (reloc_addend_value < 0xffffff00) ++ offset = offset + reloc_addend_value; + + section_size_type secn_len; ++ + const unsigned char* str_contents = + (it_v->first)->section_contents(it_v->second, + &secn_len, + false) + offset; ++ gold_assert (offset < (long long) secn_len); ++ + if ((secn_flags & elfcpp::SHF_STRINGS) != 0) + { + // String merge section. +@@ -489,10 +506,14 @@ get_section_contents(bool first_iteration, + } + else + { +- // Use the entsize to determine the length. +- buffer.append(reinterpret_cast secn_len) ++ bufsize = secn_len - offset; ++ buffer.append(reinterpret_cast(str_contents), +- entsize); ++ bufsize); + } + buffer.append("@"); + } diff --git a/gprof/ChangeLog b/gprof/ChangeLog index 9fa2109..cb3b0c3 100644 --- a/gprof/ChangeLog @@ -4086,10 +5281,116 @@ index 0aee194..87d4653 100644 2005-07-27 Jan Beulich diff --git a/ld/ChangeLog b/ld/ChangeLog -index 75fd708..e74db8c 100644 +index 75fd708..7594fac 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog -@@ -1,3 +1,194 @@ +@@ -1,3 +1,300 @@ ++2016-06-11 H.J. Lu ++ ++ Backport from master ++ 2016-04-13 H.J. Lu ++ ++ PR ld/19774 ++ * testsuite/ld-x86-64/x86-64.exp: Link tmpdir/pr17689b.o before ++ tmpdir/pr17689.so, fix gotpcrel1 test and add more --as-needed ++ tests. ++ ++ 2016-03-07 H.J. Lu ++ ++ PR ld/19774 ++ * testsuite/ld-i386/i386.exp: Link tmpdir/pr18900.o before ++ tmpdir/pr18900.so and test --as-needed. Link tmpdir/gotpc1.o ++ before tmpdir/got1d.so and test --as-needed. ++ * testsuite/ld-x86-64/x86-64.exp: Link tmpdir/pr18900.o before ++ tmpdir/pr18900.so and test --as-needed. ++ ++ 2016-03-06 H.J. Lu ++ ++ * testsuite/ld-i386/i386.exp: Link tmpdir/copyreloc-main.o ++ before tmpdir/copyreloc-lib.so and test --as-needed. ++ * testsuite/ld-x86-64/x86-64.exp: Likewise. ++ ++2016-05-20 H.J. Lu ++ ++ Backport from master ++ 2016-05-19 H.J. Lu ++ ++ PR ld/20117 ++ * testsuite/ld-i386/i386.exp: Run pr20117. ++ * testsuite/ld-i386/pr20117.d: New file. ++ * testsuite/ld-i386/pr20117.s: Likewise. ++ ++2016-05-18 Christophe Monat ++ ++ Backport from master ++ 2016-05-09 Christophe Monat ++ PR ld/20030 ++ * testsuite/ld-arm/arm-elf.exp: Run new stm32l4xx-fix-vldm-dp ++ tests. Fix misnamed stm32l4xx-fix-all. ++ * testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s: New tests for multiple ++ loads with DP registers. ++ * testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d: New reference file. ++ * testsuite/ld-arm/stm32l4xx-fix-vldm.s: Add missing comment. ++ * testsuite/ld-arm/stm32l4xx-fix-all.s: Add tests for multiple ++ loads with DP registers. ++ * testsuite/ld-arm/stm32l4xx-fix-all.d: Update reference. ++ ++2016-05-15 H.J. Lu ++ ++ Backport from master ++ 2016-05-13 H.J. Lu ++ ++ PR ld/20093 ++ * testsuite/ld-x86-64/pr20093-1.d: New file. ++ * testsuite/ld-x86-64/pr20093-1.s: Likewise. ++ * testsuite/ld-x86-64/pr20093-2.d: Likewise. ++ * testsuite/ld-x86-64/pr20093-2.s: Likewise. ++ * testsuite/ld-x86-64/x86-64.exp: Run pr20093-1 and pr20093-2. ++ ++2016-05-11 Alan Modra ++ ++ PR 20060 ++ * testsuite/ld-powerpc/powerpc.exp: Run new tests. ++ * testsuite/ld-powerpc/tlsdll.s: New. ++ * testsuite/ld-powerpc/tlsdll.ver: New. ++ * testsuite/ld-powerpc/tlsdll_32.s: New. ++ * testsuite/ld-powerpc/tlsopt5.d: New. ++ * testsuite/ld-powerpc/tlsopt5.s: New. ++ * testsuite/ld-powerpc/tlsopt5_32.d: New. ++ * testsuite/ld-powerpc/tlsopt5_32.s: New. ++ ++2016-04-30 H.J. Lu ++ ++ Backport from master ++ 2016-04-27 H.J. Lu ++ ++ PR ld/20006 ++ * testsuite/ld-elfvsb/elfvsb.exp (COMPRESS_LDFLAG): New. ++ (visibility_run): Pass COMPRESS_LDFLAG to visibility_test on ++ ELF targets. ++ ++2016-04-30 H.J. Lu ++ ++ Backport from master ++ 2016-04-27 H.J. Lu ++ ++ * testsuite/ld-elf/compressed1b.d: Only run for Linux/GNU targets. ++ ++ 2016-04-27 H.J. Lu ++ ++ * testsuite/ld-elf/compressed1b.d: Pass ++ --compress-debug-sections=none to ld. ++ * testsuite/ld-elf/compressed1c.d: Likewise. ++ ++2016-04-04 H.J. Lu ++ ++ Backport from master ++ 2016-04-04 H.J. Lu ++ ++ PR ld/19827 ++ * testsuite/ld-i386/pr19827-nacl.rd: New file. ++ * testsuite/ld-x86-64/pr19827-nacl.rd: Likewise. ++ +2016-03-17 H.J. Lu + + Backport from master @@ -4284,7 +5585,7 @@ index 75fd708..e74db8c 100644 2016-01-25 Tristan Gingold * configure: Regenerate. -@@ -89,7 +280,7 @@ +@@ -89,7 +386,7 @@ decide placement. 2015-10-27 Laurent Alfonsi @@ -4293,7 +5594,7 @@ index 75fd708..e74db8c 100644 * ld.texinfo: Add description of the STM32L4xx erratum workaround. -@@ -129,7 +320,7 @@ +@@ -129,7 +426,7 @@ 2015-10-22 H.J. Lu @@ -4302,7 +5603,7 @@ index 75fd708..e74db8c 100644 * emulparams/call_nop.sh: New file. * emulparams/elf_i386_be.sh: Source ${srcdir}/emulparams/call_nop.sh. -@@ -165,7 +356,7 @@ +@@ -165,7 +462,7 @@ 2015-10-15 Simon Dardis @@ -4311,7 +5612,7 @@ index 75fd708..e74db8c 100644 (exp_fold_tree_1): Here. Cope with ternary operator in assignments. Use new helper. -@@ -308,7 +499,7 @@ +@@ -308,7 +605,7 @@ 2015-09-09 James Bowman * scripttempl/ft32.sc: default linker script RAM and @@ -4320,7 +5621,7 @@ index 75fd708..e74db8c 100644 2015-09-09 Nick Clifton -@@ -359,58 +550,58 @@ +@@ -359,58 +656,58 @@ 2015-08-18 H.J. Lu @@ -5070,6 +6371,303 @@ index 86a070c..0000000 -bar: - ret - +diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp +index 1d9b1c8..73e1a6b 100644 +--- a/ld/testsuite/ld-arm/arm-elf.exp ++++ b/ld/testsuite/ld-arm/arm-elf.exp +@@ -167,10 +167,14 @@ set armelftests_common { + "-EL --fix-stm32l4xx-629360 -Ttext=0x8000" "" "-EL -mcpu=cortex-m4 -mfpu=fpv4-sp-d16" {stm32l4xx-fix-vldm.s} + {{objdump -dr stm32l4xx-fix-vldm.d}} + "stm32l4xx-fix-vldm"} ++ {"STM32L4XX erratum fix VLDM, DP registers" ++ "-EL --fix-stm32l4xx-629360 -Ttext=0x8000" "" "-EL -mcpu=cortex-m4 -mfpu=fpv4-sp-d16" {stm32l4xx-fix-vldm-dp.s} ++ {{objdump -dr stm32l4xx-fix-vldm-dp.d}} ++ "stm32l4xx-fix-vldm-dp"} + {"STM32L4XX erratum fix ALL" + "-EL --fix-stm32l4xx-629360=all -Ttext=0x8000" "" "-EL -mcpu=cortex-m4 -mfpu=fpv4-sp-d16" {stm32l4xx-fix-all.s} + {{objdump -dr stm32l4xx-fix-all.d}} +- "stm32l4xx-fix-vldm-all"} ++ "stm32l4xx-fix-all"} + {"STM32L4XX erratum fix in IT context" + "-EL --fix-stm32l4xx-629360 -Ttext=0x8000" "" "-EL -mcpu=cortex-m4 -mfpu=fpv4-sp-d16" {stm32l4xx-fix-it-block.s} + {{objdump -dr stm32l4xx-fix-it-block.d}} +diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-all.d b/ld/testsuite/ld-arm/stm32l4xx-fix-all.d +index 59f3ed1..c67f95d 100644 +--- a/ld/testsuite/ld-arm/stm32l4xx-fix-all.d ++++ b/ld/testsuite/ld-arm/stm32l4xx-fix-all.d +@@ -6,37 +6,37 @@ Disassembly of section \.text: + + 00008000 <__stm32l4xx_veneer_0>: + 8000: e899 01fe ldmia\.w r9, {r1, r2, r3, r4, r5, r6, r7, r8} +- 8004: f000 b84a b\.w 809c <__stm32l4xx_veneer_0_r> ++ 8004: f000 b86e b\.w 80e4 <__stm32l4xx_veneer_0_r> + 8008: f7f0 a000 udf\.w #0 + 800c: f7f0 a000 udf\.w #0 + + 00008010 <__stm32l4xx_veneer_1>: + 8010: e8b9 01fe ldmia\.w r9!, {r1, r2, r3, r4, r5, r6, r7, r8} +- 8014: f000 b844 b\.w 80a0 <__stm32l4xx_veneer_1_r> ++ 8014: f000 b868 b\.w 80e8 <__stm32l4xx_veneer_1_r> + 8018: f7f0 a000 udf\.w #0 + 801c: f7f0 a000 udf\.w #0 + + 00008020 <__stm32l4xx_veneer_2>: + 8020: e919 01fe ldmdb r9, {r1, r2, r3, r4, r5, r6, r7, r8} +- 8024: f000 b83e b\.w 80a4 <__stm32l4xx_veneer_2_r> ++ 8024: f000 b862 b\.w 80ec <__stm32l4xx_veneer_2_r> + 8028: f7f0 a000 udf\.w #0 + 802c: f7f0 a000 udf\.w #0 + + 00008030 <__stm32l4xx_veneer_3>: + 8030: e939 01fe ldmdb r9!, {r1, r2, r3, r4, r5, r6, r7, r8} +- 8034: f000 b838 b\.w 80a8 <__stm32l4xx_veneer_3_r> ++ 8034: f000 b85c b\.w 80f0 <__stm32l4xx_veneer_3_r> + 8038: f7f0 a000 udf\.w #0 + 803c: f7f0 a000 udf\.w #0 + + 00008040 <__stm32l4xx_veneer_4>: + 8040: e8bd 01fe ldmia\.w sp!, {r1, r2, r3, r4, r5, r6, r7, r8} +- 8044: f000 b832 b\.w 80ac <__stm32l4xx_veneer_4_r> ++ 8044: f000 b856 b\.w 80f4 <__stm32l4xx_veneer_4_r> + 8048: f7f0 a000 udf\.w #0 + 804c: f7f0 a000 udf\.w #0 + + 00008050 <__stm32l4xx_veneer_5>: + 8050: ecd9 0a08 vldmia r9, {s1-s8} +- 8054: f000 b82c b\.w 80b0 <__stm32l4xx_veneer_5_r> ++ 8054: f000 b850 b\.w 80f8 <__stm32l4xx_veneer_5_r> + 8058: f7f0 a000 udf\.w #0 + 805c: f7f0 a000 udf\.w #0 + 8060: f7f0 a000 udf\.w #0 +@@ -44,7 +44,7 @@ Disassembly of section \.text: + + 00008068 <__stm32l4xx_veneer_6>: + 8068: ecf6 4a08 vldmia r6!, {s9-s16} +- 806c: f000 b822 b\.w 80b4 <__stm32l4xx_veneer_6_r> ++ 806c: f000 b846 b\.w 80fc <__stm32l4xx_veneer_6_r> + 8070: f7f0 a000 udf\.w #0 + 8074: f7f0 a000 udf\.w #0 + 8078: f7f0 a000 udf\.w #0 +@@ -52,32 +52,65 @@ Disassembly of section \.text: + + 00008080 <__stm32l4xx_veneer_7>: + 8080: ecfd 0a08 vpop {s1-s8} +- 8084: f000 b818 b\.w 80b8 <__stm32l4xx_veneer_7_r> ++ 8084: f000 b83c b\.w 8100 <__stm32l4xx_veneer_7_r> + 8088: f7f0 a000 udf\.w #0 + 808c: f7f0 a000 udf\.w #0 + 8090: f7f0 a000 udf\.w #0 + 8094: f7f0 a000 udf\.w #0 + +-00008098 <_start>: +- 8098: f7ff bfb2 b\.w 8000 <__stm32l4xx_veneer_0> ++00008098 <__stm32l4xx_veneer_8>: ++ 8098: ec99 1b08 vldmia r9, {d1-d4} ++ 809c: f000 b832 b\.w 8104 <__stm32l4xx_veneer_8_r> ++ 80a0: f7f0 a000 udf\.w #0 ++ 80a4: f7f0 a000 udf\.w #0 ++ 80a8: f7f0 a000 udf\.w #0 ++ 80ac: f7f0 a000 udf\.w #0 + +-0000809c <__stm32l4xx_veneer_0_r>: +- 809c: f7ff bfb8 b\.w 8010 <__stm32l4xx_veneer_1> ++000080b0 <__stm32l4xx_veneer_9>: ++ 80b0: ecb6 8b08 vldmia r6!, {d8-d11} ++ 80b4: f000 b828 b\.w 8108 <__stm32l4xx_veneer_9_r> ++ 80b8: f7f0 a000 udf\.w #0 ++ 80bc: f7f0 a000 udf\.w #0 ++ 80c0: f7f0 a000 udf\.w #0 ++ 80c4: f7f0 a000 udf\.w #0 + +-000080a0 <__stm32l4xx_veneer_1_r>: +- 80a0: f7ff bfbe b\.w 8020 <__stm32l4xx_veneer_2> ++000080c8 <__stm32l4xx_veneer_a>: ++ 80c8: ecbd 1b08 vpop {d1-d4} ++ 80cc: f000 b81e b\.w 810c <__stm32l4xx_veneer_a_r> ++ 80d0: f7f0 a000 udf\.w #0 ++ 80d4: f7f0 a000 udf\.w #0 ++ 80d8: f7f0 a000 udf\.w #0 ++ 80dc: f7f0 a000 udf\.w #0 + +-000080a4 <__stm32l4xx_veneer_2_r>: +- 80a4: f7ff bfc4 b\.w 8030 <__stm32l4xx_veneer_3> ++000080e0 <_start>: ++ 80e0: f7ff bf8e b\.w 8000 <__stm32l4xx_veneer_0> + +-000080a8 <__stm32l4xx_veneer_3_r>: +- 80a8: f7ff bfca b\.w 8040 <__stm32l4xx_veneer_4> ++000080e4 <__stm32l4xx_veneer_0_r>: ++ 80e4: f7ff bf94 b\.w 8010 <__stm32l4xx_veneer_1> + +-000080ac <__stm32l4xx_veneer_4_r>: +- 80ac: f7ff bfd0 b\.w 8050 <__stm32l4xx_veneer_5> ++000080e8 <__stm32l4xx_veneer_1_r>: ++ 80e8: f7ff bf9a b\.w 8020 <__stm32l4xx_veneer_2> + +-000080b0 <__stm32l4xx_veneer_5_r>: +- 80b0: f7ff bfda b\.w 8068 <__stm32l4xx_veneer_6> ++000080ec <__stm32l4xx_veneer_2_r>: ++ 80ec: f7ff bfa0 b\.w 8030 <__stm32l4xx_veneer_3> + +-000080b4 <__stm32l4xx_veneer_6_r>: +- 80b4: f7ff bfe4 b\.w 8080 <__stm32l4xx_veneer_7> ++000080f0 <__stm32l4xx_veneer_3_r>: ++ 80f0: f7ff bfa6 b\.w 8040 <__stm32l4xx_veneer_4> ++ ++000080f4 <__stm32l4xx_veneer_4_r>: ++ 80f4: f7ff bfac b\.w 8050 <__stm32l4xx_veneer_5> ++ ++000080f8 <__stm32l4xx_veneer_5_r>: ++ 80f8: f7ff bfb6 b\.w 8068 <__stm32l4xx_veneer_6> ++ ++000080fc <__stm32l4xx_veneer_6_r>: ++ 80fc: f7ff bfc0 b\.w 8080 <__stm32l4xx_veneer_7> ++ ++00008100 <__stm32l4xx_veneer_7_r>: ++ 8100: f7ff bfca b\.w 8098 <__stm32l4xx_veneer_8> ++ ++00008104 <__stm32l4xx_veneer_8_r>: ++ 8104: f7ff bfd4 b\.w 80b0 <__stm32l4xx_veneer_9> ++ ++00008108 <__stm32l4xx_veneer_9_r>: ++ 8108: f7ff bfde b\.w 80c8 <__stm32l4xx_veneer_a> +diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-all.s b/ld/testsuite/ld-arm/stm32l4xx-fix-all.s +index 0c18266..580e5b2 100644 +--- a/ld/testsuite/ld-arm/stm32l4xx-fix-all.s ++++ b/ld/testsuite/ld-arm/stm32l4xx-fix-all.s +@@ -20,3 +20,6 @@ _start: + vldm r9, {s1-s8} + vldm r6!, {s9-s16} + vpop {s1-s8} ++ vldm r9, {d1-d4} ++ vldm r6!, {d8-d11} ++ vpop {d1-d4} +diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d +new file mode 100644 +index 0000000..cd7de14 +--- /dev/null ++++ b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d +@@ -0,0 +1,49 @@ ++ ++.*: file format elf32-littlearm.* ++ ++ ++Disassembly of section \.text: ++ ++00008000 <__stm32l4xx_veneer_0>: ++ 8000: ecba 1b08 vldmia sl!, {d1-d4} ++ 8004: ecba 5b08 vldmia sl!, {d5-d8} ++ 8008: ecba 9b08 vldmia sl!, {d9-d12} ++ 800c: ecba db06 vldmia sl!, {d13-d15} ++ 8010: f1aa 0a78 sub\.w sl, sl, #120 ; 0x78 ++ 8014: f000 b826 b\.w 8064 <__stm32l4xx_veneer_0_r> ++ ++00008018 <__stm32l4xx_veneer_1>: ++ 8018: ecb7 5b08 vldmia r7!, {d5-d8} ++ 801c: ecb7 9b08 vldmia r7!, {d9-d12} ++ 8020: ecb7 db06 vldmia r7!, {d13-d15} ++ 8024: f000 b820 b\.w 8068 <__stm32l4xx_veneer_1_r> ++ 8028: f7f0 a000 udf\.w #0 ++ 802c: f7f0 a000 udf\.w #0 ++ ++00008030 <__stm32l4xx_veneer_2>: ++ 8030: ecbd 1b08 vpop {d1-d4} ++ 8034: ecbd 5b02 vpop {d5} ++ 8038: f000 b818 b\.w 806c <__stm32l4xx_veneer_2_r> ++ 803c: f7f0 a000 udf\.w #0 ++ 8040: f7f0 a000 udf\.w #0 ++ 8044: f7f0 a000 udf\.w #0 ++ ++00008048 <__stm32l4xx_veneer_3>: ++ 8048: ed3c 1b08 vldmdb ip!, {d1-d4} ++ 804c: ed3c 5b08 vldmdb ip!, {d5-d8} ++ 8050: ed3c 9b08 vldmdb ip!, {d9-d12} ++ 8054: ed3c db06 vldmdb ip!, {d13-d15} ++ 8058: f000 b80a b\.w 8070 <__stm32l4xx_veneer_3_r> ++ 805c: f7f0 a000 udf\.w #0 ++ ++00008060 <_start>: ++ 8060: f7ff bfce b\.w 8000 <__stm32l4xx_veneer_0> ++ ++00008064 <__stm32l4xx_veneer_0_r>: ++ 8064: f7ff bfd8 b\.w 8018 <__stm32l4xx_veneer_1> ++ ++00008068 <__stm32l4xx_veneer_1_r>: ++ 8068: f7ff bfe2 b\.w 8030 <__stm32l4xx_veneer_2> ++ ++0000806c <__stm32l4xx_veneer_2_r>: ++ 806c: f7ff bfec b\.w 8048 <__stm32l4xx_veneer_3> +diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s +new file mode 100644 +index 0000000..7c7ce01 +--- /dev/null ++++ b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s +@@ -0,0 +1,27 @@ ++ .syntax unified ++ .cpu cortex-m4 ++ .fpu fpv4-sp-d16 ++ .text ++ .align 1 ++ .thumb ++ .thumb_func ++ .global _start ++_start: ++ @ VLDM CASE #1 ++ @ vldm rx, {...} ++ @ -> vldm rx!, {8_words_or_less} for each ++ @ -> sub rx, rx, #size (list) ++ vldm r10, {d1-d15} ++ ++ @ VLDM CASE #2 ++ @ vldm rx!, {...} ++ @ -> vldm rx!, {8_words_or_less} for each needed 8_word ++ @ This also handles vpop instruction (when rx is sp) ++ vldm r7!, {d5-d15} ++ @ Explicit VPOP test ++ vpop {d1-d5} ++ ++ @ VLDM CASE #3 ++ @ vldmd rx!, {...} ++ @ -> vldmb rx!, {8_words_or_less} for each needed 8_word ++ vldmdb r12!, {d1-d15} +diff --git a/ld/testsuite/ld-arm/stm32l4xx-fix-vldm.s b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm.s +index 94aa66e..b072801 100644 +--- a/ld/testsuite/ld-arm/stm32l4xx-fix-vldm.s ++++ b/ld/testsuite/ld-arm/stm32l4xx-fix-vldm.s +@@ -21,6 +21,7 @@ _start: + @ Explicit VPOP test + vpop {s1-s9} + ++ @ VLDM CASE #3 + @ vldmd rx!, {...} + @ -> vldmb rx!, {8_words_or_less} for each needed 8_word + vldmdb r11!, {s1-s31} +diff --git a/ld/testsuite/ld-elf/compressed1b.d b/ld/testsuite/ld-elf/compressed1b.d +index 83dc60f..34dfe8e 100644 +--- a/ld/testsuite/ld-elf/compressed1b.d ++++ b/ld/testsuite/ld-elf/compressed1b.d +@@ -1,7 +1,8 @@ + #source: compress1.s + #as: --compress-debug-sections=zlib-gabi +-#ld: -r ++#ld: -r --compress-debug-sections=none + #readelf: -t ++#target: *-*-linux* *-*-gnu* + + #failif + #... +diff --git a/ld/testsuite/ld-elf/compressed1c.d b/ld/testsuite/ld-elf/compressed1c.d +index 64f75be..29e91da 100644 +--- a/ld/testsuite/ld-elf/compressed1c.d ++++ b/ld/testsuite/ld-elf/compressed1c.d +@@ -1,6 +1,6 @@ + #source: compress1.s + #as: --compress-debug-sections=zlib-gabi +-#ld: -shared ++#ld: -shared --compress-debug-sections=none + #readelf: -t + #target: *-*-linux* *-*-gnu* + diff --git a/ld/testsuite/ld-elf/gabiend.rt b/ld/testsuite/ld-elf/gabiend.rt index 23bc36c..75b5ba7 100644 --- a/ld/testsuite/ld-elf/gabiend.rt @@ -5384,6 +6982,35 @@ index 731eef3..b8c12cb 100644 + ] \ ] } +diff --git a/ld/testsuite/ld-elfvsb/elfvsb.exp b/ld/testsuite/ld-elfvsb/elfvsb.exp +index e02d4fa..4766d0e 100644 +--- a/ld/testsuite/ld-elfvsb/elfvsb.exp ++++ b/ld/testsuite/ld-elfvsb/elfvsb.exp +@@ -62,6 +62,7 @@ if ![isnative] then {return} + set tmpdir tmpdir + set SHCFLAG "" + set shared_needs_pic "no" ++set COMPRESS_LDFLAG "-Wl,--compress-debug-sections=zlib-gabi" + + if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } { + +@@ -228,6 +229,7 @@ proc visibility_run {visibility} { + global support_protected + global shared_needs_pic + global PLT_CFLAGS ++ global COMPRESS_LDFLAG + + if [ string match $visibility "hidden" ] { + set VSBCFLAG "-DHIDDEN_TEST" +@@ -384,7 +386,7 @@ proc visibility_run {visibility} { + } else { if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } { + visibility_test $visibility vp "visibility ($visibility)" mainnp.o sh1p.o sh2p.o xcoff + } else { +- visibility_test $visibility vp "visibility ($visibility)" mainnp.o sh1p.o sh2p.o elfvsb ++ visibility_test $visibility vp "visibility ($visibility)" mainnp.o sh1p.o sh2p.o elfvsb $COMPRESS_LDFLAG + } } + } + }} diff --git a/ld/testsuite/ld-i386/branch1.d b/ld/testsuite/ld-i386/branch1.d index a078f1d..81b069e 100644 --- a/ld/testsuite/ld-i386/branch1.d @@ -5551,7 +7178,7 @@ index a6d51c6..7e4c9b1 100644 subl $20, %esp leal __FUNCTION__.1866@GOTOFF(%ebx), %esi diff --git a/ld/testsuite/ld-i386/i386.exp b/ld/testsuite/ld-i386/i386.exp -index fb1d3ea..1916c24 100644 +index fb1d3ea..be45649 100644 --- a/ld/testsuite/ld-i386/i386.exp +++ b/ld/testsuite/ld-i386/i386.exp @@ -195,6 +195,14 @@ set i386tests { @@ -5569,15 +7196,16 @@ index fb1d3ea..1916c24 100644 } # So as to avoid rewriting every last test case here in a nacl variant, -@@ -319,6 +327,7 @@ run_dump_test "load5a" +@@ -319,6 +327,8 @@ run_dump_test "load5a" run_dump_test "load5b" run_dump_test "load6" run_dump_test "pr19175" +run_dump_test "pr19615" ++run_dump_test "pr20117" if { !([istarget "i?86-*-linux*"] || [istarget "i?86-*-gnu*"] -@@ -357,7 +366,7 @@ if { [isnative] +@@ -357,7 +367,7 @@ if { [isnative] [list \ "Build libplt-main1.a" \ "" \ @@ -5586,7 +7214,7 @@ index fb1d3ea..1916c24 100644 { plt-main1.c } \ {{readelf {-Wr} plt-main1.rd}} \ "libplt-main1.a" \ -@@ -365,7 +374,7 @@ if { [isnative] +@@ -365,7 +375,7 @@ if { [isnative] [list \ "Build libplt-main2.a" \ "" \ @@ -5595,7 +7223,7 @@ index fb1d3ea..1916c24 100644 { plt-main2.c } \ {{readelf {-Wr} plt-main2.rd}} \ "libplt-main2.a" \ -@@ -373,7 +382,7 @@ if { [isnative] +@@ -373,7 +383,7 @@ if { [isnative] [list \ "Build libplt-main3.a" \ "" \ @@ -5604,7 +7232,7 @@ index fb1d3ea..1916c24 100644 { plt-main3.c } \ {{readelf {-Wr} plt-main3.rd}} \ "libplt-main3.a" \ -@@ -381,7 +390,7 @@ if { [isnative] +@@ -381,7 +391,7 @@ if { [isnative] [list \ "Build libplt-main4.a" \ "" \ @@ -5613,15 +7241,113 @@ index fb1d3ea..1916c24 100644 { plt-main4.c } \ {{readelf {-Wr} plt-main4.rd}} \ "libplt-main4.a" \ -@@ -535,7 +544,7 @@ if { [isnative] +@@ -413,18 +423,26 @@ if { [isnative] + "copyreloc-lib.so" \ + ] \ [list \ - "Build gotpc1" \ - "tmpdir/got1d.so" \ -- "" \ -+ "-Wa,-mrelax-relocations=yes" \ +- "Build copyreloc-main with PIE and GOTOFF (1)" \ +- "tmpdir/copyreloc-lib.so -pie" \ ++ "Build libcopyreloc-main.a" \ ++ "" \ + "" \ + { copyreloc-main.S } \ ++ {} \ ++ "libcopyreloc-main.a" \ ++ ] \ ++ [list \ ++ "Build copyreloc-main with PIE and GOTOFF (1)" \ ++ "tmpdir/copyreloc-main.o tmpdir/copyreloc-lib.so -pie" \ ++ "" \ ++ { dummy.s } \ + {{readelf {-Wr} copyreloc-main1.rd}} \ + "copyreloc-main" \ + ] \ + [list \ + "Build copyreloc-main with PIE and GOTOFF (2)" \ +- "tmpdir/copyreloc-lib.so -pie" \ ++ "tmpdir/copyreloc-main.o tmpdir/copyreloc-lib.so -pie" \ + "" \ +- { copyreloc-main.S } \ ++ { dummy.s } \ + {{readelf {-Wr} copyreloc-main2.rd}} \ + "copyreloc-main" \ + ] \ +@@ -501,18 +519,26 @@ if { [isnative] + "pr18900.so" \ + ] \ + [list \ +- "Build pr18900a" \ +- "tmpdir/pr18900.so" \ ++ "Build pr18900.o" \ ++ "-r -nostdlib" \ + "" \ + { pr18900b.c pr18900c.c } \ ++ "" \ ++ "pr18900.o" \ ++ ] \ ++ [list \ ++ "Build pr18900a" \ ++ "tmpdir/pr18900.o tmpdir/pr18900.so" \ ++ "" \ ++ { dummy.s } \ + {{readelf {-Wrd} pr18900a.rd}} \ + "pr18900a" \ + ] \ + [list \ + "Build pr18900b" \ +- "tmpdir/pr18900.so" \ ++ "-Wl,--as-needed tmpdir/pr18900.o tmpdir/pr18900.so" \ + "" \ +- { pr18900b.c pr18900c.c } \ ++ { dummy.s } \ + {{readelf {-Wrd} pr18900b.rd}} \ + "pr18900b" \ + ] \ +@@ -533,10 +559,18 @@ if { [isnative] + "got1d.so" \ + ] \ + [list \ +- "Build gotpc1" \ +- "tmpdir/got1d.so" \ ++ "Build gotpc1.o" \ ++ "-r -nostdlib" \ + "" \ { got1a.S got1b.c got1c.c } \ ++ "" \ ++ "gotpc1.o" \ ++ ] \ ++ [list \ ++ "Build gotpc1" \ ++ "-Wl,--as-needed tmpdir/gotpc1.o tmpdir/got1d.so" \ ++ "-Wa,-mrelax-relocations=yes" \ ++ { dummy.s } \ {{objdump {-dw} got1.dd}} \ "got1" \ + ] \ +@@ -580,9 +614,9 @@ if { [isnative] + ] \ + [list \ + "Run copyreloc-main with PIE and GOTOFF" \ +- "tmpdir/copyreloc-lib.so -pie" \ ++ "--as-needed tmpdir/copyreloc-main.o tmpdir/copyreloc-lib.so -pie" \ + "" \ +- { copyreloc-main.S } \ ++ { dummy.s } \ + "copyreloc-main" \ + "copyreloc-main.out" \ + ] \ +@@ -612,9 +646,9 @@ if { [isnative] + ] \ + [list \ + "Run pr18900" \ +- "tmpdir/pr18900.so" \ ++ "tmpdir/pr18900.o tmpdir/pr18900.so" \ + "" \ +- { pr18900b.c pr18900c.c } \ ++ { dummy.s } \ + "pr18900" \ + "pr18900.out" \ + ] \ diff --git a/ld/testsuite/ld-i386/jmp1.d b/ld/testsuite/ld-i386/jmp1.d index 69383b2..e3ebedc 100644 --- a/ld/testsuite/ld-i386/jmp1.d @@ -5758,6 +7484,17 @@ index 0000000..1d85926 + + .section ".xyzzy_ptr","aw",%progbits + .dc.a xyzzy +diff --git a/ld/testsuite/ld-i386/pr19827-nacl.rd b/ld/testsuite/ld-i386/pr19827-nacl.rd +new file mode 100644 +index 0000000..5d2a885 +--- /dev/null ++++ b/ld/testsuite/ld-i386/pr19827-nacl.rd +@@ -0,0 +1,5 @@ ++#readelf: -r --wide ++ ++Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 1 entries: ++ Offset Info Type Sym. Value Symbol's Name ++[0-9a-f]+ +[0-9a-f]+ +R_386_RELATIVE + diff --git a/ld/testsuite/ld-i386/pr19827.rd b/ld/testsuite/ld-i386/pr19827.rd new file mode 100644 index 0000000..5d2a885 @@ -5791,6 +7528,37 @@ index 0000000..bb46e1d @@ -0,0 +1,2 @@ + .data + .dc.a foo +diff --git a/ld/testsuite/ld-i386/pr20117.d b/ld/testsuite/ld-i386/pr20117.d +new file mode 100644 +index 0000000..59c77ee +--- /dev/null ++++ b/ld/testsuite/ld-i386/pr20117.d +@@ -0,0 +1,12 @@ ++#as: --32 ++#ld: -melf_i386 ++#objdump: -dw ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++[a-f0-9]+ <_start>: ++[ ]*[a-f0-9]+: eb 8b jmp [a-f0-9]+ <_start\-0x[a-f0-9]+> ++[ ]*[a-f0-9]+: bd ([0-9a-f]{2} ){4} * mov \$0x[a-f0-9]+\,%ebp +diff --git a/ld/testsuite/ld-i386/pr20117.s b/ld/testsuite/ld-i386/pr20117.s +new file mode 100644 +index 0000000..de2dd28 +--- /dev/null ++++ b/ld/testsuite/ld-i386/pr20117.s +@@ -0,0 +1,7 @@ ++ .comm DEBUGLEVEL,4,4 ++ .text ++ .globl _start ++ .type _start, @function ++_start: ++ .byte 0xeb, 0x8b ++ movl $DEBUGLEVEL@GOT, %ebp diff --git a/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d b/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d index 53ccd5a..ae75487 100644 --- a/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d @@ -5848,6 +7616,235 @@ index 81e72b4..982ffee 100644 } { fail $testname } +diff --git a/ld/testsuite/ld-powerpc/powerpc.exp b/ld/testsuite/ld-powerpc/powerpc.exp +index efb4026..6f9c8ed 100644 +--- a/ld/testsuite/ld-powerpc/powerpc.exp ++++ b/ld/testsuite/ld-powerpc/powerpc.exp +@@ -138,6 +138,11 @@ set ppcelftests { + {"TLS32 opt 4" "-melf32ppc" "" "-a32" {tlsopt4_32.s tlslib32.s} + {{objdump -dr tlsopt4_32.d}} + "tlsopt4_32"} ++ {"TLS32 DLL" "-shared -melf32ppc --version-script tlsdll.ver" "" "-a32" {tlsdll_32.s} ++ {} "tlsdll32.so"} ++ {"TLS32 opt 5" "-melf32ppc --gc-sections --secure-plt tmpdir/tlsdll32.so" "" "-a32" {tlsopt5_32.s} ++ {{objdump -dr tlsopt5_32.d}} ++ "tlsopt5_32"} + {"Shared library with global symbol" "-shared -melf32ppc" "" "-a32" {sdalib.s} + {} "sdalib.so"} + {"Dynamic application with SDA" "-melf32ppc tmpdir/sdalib.so" "" "-a32" {sdadyn.s} +@@ -203,6 +208,11 @@ set ppc64elftests { + {"TLS opt 4" "-melf64ppc" "" "-a64" {tlsopt4.s tlslib.s} + {{objdump -dr tlsopt4.d}} + "tlsopt4"} ++ {"TLS DLL" "-shared -melf64ppc --version-script tlsdll.ver" "" "-a64" {tlsdll.s} ++ {} "tlsdll.so"} ++ {"TLS opt 5" "-melf64ppc --gc-sections tmpdir/tlsdll.so" "" "-a64" {tlsopt5.s} ++ {{objdump -dr tlsopt5.d}} ++ "tlsopt5"} + {"sym@tocbase" "-shared -melf64ppc" "" "-a64" {symtocbase-1.s symtocbase-2.s} + {{objdump -dj.data symtocbase.d}} "symtocbase.so"} + {"TOC opt" "-melf64ppc" "" "-a64" {tocopt.s} +diff --git a/ld/testsuite/ld-powerpc/tlsdll.s b/ld/testsuite/ld-powerpc/tlsdll.s +new file mode 100644 +index 0000000..5620080 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/tlsdll.s +@@ -0,0 +1,19 @@ ++ .abiversion 2 ++ .global __tls_get_addr,__tls_get_addr_opt,gd,ld ++ .type __tls_get_addr,@function ++ .type __tls_get_addr_opt,@function ++ ++ .text ++__tls_get_addr: ++__tls_get_addr_opt: ++ blr ++ .size __tls_get_addr,. - __tls_get_addr ++ .size __tls_get_addr_opt,. - __tls_get_addr_opt ++ ++ .section ".tbss","awT",@nobits ++ .p2align 3 ++gd: .space 8 ++ ++ .section ".tdata","awT",@progbits ++ .p2align 2 ++ld: .long 0xc0ffee +diff --git a/ld/testsuite/ld-powerpc/tlsdll.ver b/ld/testsuite/ld-powerpc/tlsdll.ver +new file mode 100644 +index 0000000..d9439f7 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/tlsdll.ver +@@ -0,0 +1,7 @@ ++GLIBC_2.3 { ++ __tls_get_addr; ++}; ++ ++GLIBC_2.22 { ++ __tls_get_addr_opt; ++} GLIBC_2.3; +diff --git a/ld/testsuite/ld-powerpc/tlsdll_32.s b/ld/testsuite/ld-powerpc/tlsdll_32.s +new file mode 100644 +index 0000000..0f68c21 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/tlsdll_32.s +@@ -0,0 +1,18 @@ ++ .global __tls_get_addr,__tls_get_addr_opt,gd,ld ++ .type __tls_get_addr,@function ++ .type __tls_get_addr_opt,@function ++ ++ .text ++__tls_get_addr: ++__tls_get_addr_opt: ++ blr ++ .size __tls_get_addr,. - __tls_get_addr ++ .size __tls_get_addr_opt,. - __tls_get_addr_opt ++ ++ .section ".tbss","awT",@nobits ++ .p2align 2 ++gd: .space 4 ++ ++ .section ".tdata","awT",@progbits ++ .p2align 2 ++ld: .long 0xc0ffee +diff --git a/ld/testsuite/ld-powerpc/tlsopt5.d b/ld/testsuite/ld-powerpc/tlsopt5.d +new file mode 100644 +index 0000000..7b17130 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/tlsopt5.d +@@ -0,0 +1,54 @@ ++#source: tlsopt5.s ++#as: -a64 ++#ld: --gc-sections tlsdll.so ++#objdump: -dr ++#target: powerpc64*-*-* ++ ++.* ++ ++Disassembly of section \.text: ++ ++0000000010000300 <.*\.plt_call\.__tls_get_addr_opt@@GLIBC_2\.22>: ++.*: (00 00 63 e9|e9 63 00 00) ld r11,0\(r3\) ++.*: (08 00 83 e9|e9 83 00 08) ld r12,8\(r3\) ++.*: (78 1b 60 7c|7c 60 1b 78) mr r0,r3 ++.*: (00 00 2b 2c|2c 2b 00 00) cmpdi r11,0 ++.*: (14 6a 6c 7c|7c 6c 6a 14) add r3,r12,r13 ++.*: (20 00 82 4d|4d 82 00 20) beqlr ++.*: (78 03 03 7c|7c 03 03 78) mr r3,r0 ++.*: (a6 02 68 7d|7d 68 02 a6) mflr r11 ++.*: (08 00 61 f9|f9 61 00 08) std r11,8\(r1\) ++.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) ++.*: (28 80 82 e9|e9 82 80 28) ld r12,-32728\(r2\) ++.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 ++.*: (21 04 80 4e|4e 80 04 21) bctrl ++.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\) ++.*: (08 00 61 e9|e9 61 00 08) ld r11,8\(r1\) ++.*: (a6 03 68 7d|7d 68 03 a6) mtlr r11 ++.*: (20 00 80 4e|4e 80 00 20) blr ++ ++0000000010000344 <_start>: ++.*: (08 80 62 38|38 62 80 08) addi r3,r2,-32760 ++.*: (b9 ff ff 4b|4b ff ff b9) bl .* ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (b8 02 01 00|00 00 00 00) .* ++.*: (00 00 00 00|00 01 02 b8) .* ++ ++0000000010000358 <__glink_PLTresolve>: ++.*: (a6 02 08 7c|7c 08 02 a6) mflr r0 ++.*: (05 00 9f 42|42 9f 00 05) bcl .* ++.*: (a6 02 68 7d|7d 68 02 a6) mflr r11 ++.*: (f0 ff 4b e8|e8 4b ff f0) ld r2,-16\(r11\) ++.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0 ++.*: (50 60 8b 7d|7d 8b 60 50) subf r12,r11,r12 ++.*: (14 5a 62 7d|7d 62 5a 14) add r11,r2,r11 ++.*: (d0 ff 0c 38|38 0c ff d0) addi r0,r12,-48 ++.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\) ++.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2 ++.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 ++.*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\) ++.*: (20 04 80 4e|4e 80 04 20) bctr ++.*: (00 00 00 60|60 00 00 00) nop ++ ++0000000010000390 <__tls_get_addr_opt@plt>: ++.*: (c8 ff ff 4b|4b ff ff c8) b .* +diff --git a/ld/testsuite/ld-powerpc/tlsopt5.s b/ld/testsuite/ld-powerpc/tlsopt5.s +new file mode 100644 +index 0000000..598bbd9 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/tlsopt5.s +@@ -0,0 +1,5 @@ ++ .globl _start ++_start: ++ addi 3,2,gd@got@tlsgd ++ bl __tls_get_addr(gd@tlsgd) ++ nop +diff --git a/ld/testsuite/ld-powerpc/tlsopt5_32.d b/ld/testsuite/ld-powerpc/tlsopt5_32.d +new file mode 100644 +index 0000000..9749248 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/tlsopt5_32.d +@@ -0,0 +1,52 @@ ++#source: tlsopt5_32.s ++#as: -a32 ++#ld: --gc-sections --secure-plt tlsdll32.so ++#objdump: -dr ++#target: powerpc*-*-* ++ ++.* ++ ++Disassembly of section \.text: ++ ++01800230 <_start>: ++.*: (f8 ff 6d 38|38 6d ff f8) addi r3,r13,-8 ++.*: (0d 00 00 48|48 00 00 0d) bl 1800240 <__tls_get_addr_opt@plt> ++ \.\.\. ++ ++01800240 <__tls_get_addr_opt@plt>: ++.*: (00 00 63 81|81 63 00 00) lwz r11,0\(r3\) ++.*: (04 00 83 81|81 83 00 04) lwz r12,4\(r3\) ++.*: (78 1b 60 7c|7c 60 1b 78) mr r0,r3 ++.*: (00 00 0b 2c|2c 0b 00 00) cmpwi r11,0 ++.*: (14 12 6c 7c|7c 6c 12 14) add r3,r12,r2 ++.*: (20 00 82 4d|4d 82 00 20) beqlr ++.*: (78 03 03 7c|7c 03 03 78) mr r3,r0 ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (81 01 60 3d|3d 60 01 81) lis r11,385 ++.*: (9c 03 6b 81|81 6b 03 9c) lwz r11,924\(r11\) ++.*: (a6 03 69 7d|7d 69 03 a6) mtctr r11 ++.*: (20 04 80 4e|4e 80 04 20) bctr ++ ++01800270 <__glink>: ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop ++ ++01800280 <__glink_PLTresolve>: ++.*: (81 01 80 3d|3d 80 01 81) lis r12,385 ++.*: (80 fe 6b 3d|3d 6b fe 80) addis r11,r11,-384 ++.*: (94 03 0c 80|80 0c 03 94) lwz r0,916\(r12\) ++.*: (90 fd 6b 39|39 6b fd 90) addi r11,r11,-624 ++.*: (a6 03 09 7c|7c 09 03 a6) mtctr r0 ++.*: (14 5a 0b 7c|7c 0b 5a 14) add r0,r11,r11 ++.*: (98 03 8c 81|81 8c 03 98) lwz r12,920\(r12\) ++.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11 ++.*: (20 04 80 4e|4e 80 04 20) bctr ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop ++.*: (00 00 00 60|60 00 00 00) nop +diff --git a/ld/testsuite/ld-powerpc/tlsopt5_32.s b/ld/testsuite/ld-powerpc/tlsopt5_32.s +new file mode 100644 +index 0000000..36b4858 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/tlsopt5_32.s +@@ -0,0 +1,4 @@ ++ .globl _start ++_start: ++ addi 3,13,gd@got@tlsgd ++ bl __tls_get_addr(gd@tlsgd) diff --git a/ld/testsuite/ld-x86-64/call1a.d b/ld/testsuite/ld-x86-64/call1a.d index 2a63b1c..2b131ee 100644 --- a/ld/testsuite/ld-x86-64/call1a.d @@ -6039,6 +8036,17 @@ index 0000000..1d85926 + + .section ".xyzzy_ptr","aw",%progbits + .dc.a xyzzy +diff --git a/ld/testsuite/ld-x86-64/pr19827-nacl.rd b/ld/testsuite/ld-x86-64/pr19827-nacl.rd +new file mode 100644 +index 0000000..67eaacc +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr19827-nacl.rd +@@ -0,0 +1,5 @@ ++#readelf: -r --wide ++ ++Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries: ++ Offset Info Type Symbol's Value Symbol's Name \+ Addend ++[0-9a-f]+ +[0-9a-f]+ +R_X86_64_RELATIVE +[0-9a-f]+ diff --git a/ld/testsuite/ld-x86-64/pr19827.rd b/ld/testsuite/ld-x86-64/pr19827.rd new file mode 100644 index 0000000..67eaacc @@ -6072,8 +8080,74 @@ index 0000000..bb46e1d @@ -0,0 +1,2 @@ + .data + .dc.a foo +diff --git a/ld/testsuite/ld-x86-64/pr20093-1.d b/ld/testsuite/ld-x86-64/pr20093-1.d +new file mode 100644 +index 0000000..de81443 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr20093-1.d +@@ -0,0 +1,11 @@ ++#as: --64 ++#ld: -pie -melf_x86_64 ++#objdump: -dw ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++[a-f0-9]+ <_start>: ++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+> +diff --git a/ld/testsuite/ld-x86-64/pr20093-1.s b/ld/testsuite/ld-x86-64/pr20093-1.s +new file mode 100644 +index 0000000..c86a21e +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr20093-1.s +@@ -0,0 +1,11 @@ ++ .section .lbss,"aw",@nobits ++foo1: ++ .space 1073741824 ++ .space 1073741824 ++ .space 1073741824 ++ .text ++ .globl _start ++ .type _start, @function ++_start: ++ movq foo1@GOTPCREL(%rip), %rax ++ .size _start, .-_start +diff --git a/ld/testsuite/ld-x86-64/pr20093-2.d b/ld/testsuite/ld-x86-64/pr20093-2.d +new file mode 100644 +index 0000000..de81443 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr20093-2.d +@@ -0,0 +1,11 @@ ++#as: --64 ++#ld: -pie -melf_x86_64 ++#objdump: -dw ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++[a-f0-9]+ <_start>: ++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+> +diff --git a/ld/testsuite/ld-x86-64/pr20093-2.s b/ld/testsuite/ld-x86-64/pr20093-2.s +new file mode 100644 +index 0000000..cfbe9c2 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/pr20093-2.s +@@ -0,0 +1,9 @@ ++ .largecomm foo1,1073741824,32 ++ .largecomm foo2,1073741824,32 ++ .largecomm foo3,1073741824,32 ++ .text ++ .globl _start ++ .type _start, @function ++_start: ++ movq foo1@GOTPCREL(%rip), %rax ++ .size _start, .-_start diff --git a/ld/testsuite/ld-x86-64/x86-64.exp b/ld/testsuite/ld-x86-64/x86-64.exp -index 45b7f09..378c13f 100644 +index 45b7f09..484d5e3 100644 --- a/ld/testsuite/ld-x86-64/x86-64.exp +++ b/ld/testsuite/ld-x86-64/x86-64.exp @@ -148,6 +148,14 @@ set x86_64tests { @@ -6091,7 +8165,16 @@ index 45b7f09..378c13f 100644 } # So as to avoid rewriting every last test case here in a nacl variant, -@@ -353,6 +361,8 @@ run_dump_test "pr19013-x32" +@@ -239,6 +247,8 @@ run_dump_test "pr14215" + run_dump_test "pr14207" + run_dump_test "gotplt1" + run_dump_test "pie1" ++run_dump_test "pr20093-1" ++run_dump_test "pr20093-2" + + if { ![istarget "x86_64-*-linux*"] && ![istarget "x86_64-*-nacl*"]} { + return +@@ -353,6 +363,8 @@ run_dump_test "pr19013-x32" run_dump_test "pr19013-nacl" run_dump_test "pr19162" run_dump_test "pr19175" @@ -6100,7 +8183,7 @@ index 45b7f09..378c13f 100644 # Add $PLT_CFLAGS if PLT is expected. global PLT_CFLAGS -@@ -391,7 +401,7 @@ if { [isnative] && [which $CC] != 0 } { +@@ -391,7 +403,7 @@ if { [isnative] && [which $CC] != 0 } { [list \ "Build libplt-main1.a" \ "" \ @@ -6109,7 +8192,7 @@ index 45b7f09..378c13f 100644 { plt-main1.c } \ {{readelf {-Wr} plt-main1.rd}} \ "libplt-main1.a" \ -@@ -399,7 +409,7 @@ if { [isnative] && [which $CC] != 0 } { +@@ -399,7 +411,7 @@ if { [isnative] && [which $CC] != 0 } { [list \ "Build libplt-main2.a" \ "" \ @@ -6118,7 +8201,7 @@ index 45b7f09..378c13f 100644 { plt-main2.c } \ {{readelf {-Wr} plt-main2.rd}} \ "libplt-main2.a" \ -@@ -407,7 +417,7 @@ if { [isnative] && [which $CC] != 0 } { +@@ -407,7 +419,7 @@ if { [isnative] && [which $CC] != 0 } { [list \ "Build libplt-main3.a" \ "" \ @@ -6127,7 +8210,7 @@ index 45b7f09..378c13f 100644 { plt-main3.c } \ {{readelf {-Wr} plt-main3.rd}} \ "libplt-main3.a" \ -@@ -415,7 +425,7 @@ if { [isnative] && [which $CC] != 0 } { +@@ -415,7 +427,7 @@ if { [isnative] && [which $CC] != 0 } { [list \ "Build libplt-main4.a" \ "" \ @@ -6136,20 +8219,193 @@ index 45b7f09..378c13f 100644 { plt-main4.c } \ {{readelf {-Wr} plt-main4.rd}} \ "libplt-main4.a" \ -@@ -545,7 +555,7 @@ if { [isnative] && [which $CC] != 0 } { +@@ -447,18 +459,26 @@ if { [isnative] && [which $CC] != 0 } { + "copyreloc-lib.so" \ + ] \ [list \ - "Build gotpcrel1" \ - "tmpdir/gotpcrel1d.so" \ -- "" \ -+ "-Wa,-mrelax-relocations=yes" \ +- "Build copyreloc-main with PIE without -fPIE (1)" \ +- "tmpdir/copyreloc-lib.so -pie" \ ++ "Build libcopyreloc-main.a" \ ++ "" \ + "" \ + { copyreloc-main.S } \ ++ {} \ ++ "libcopyreloc-main.a" \ ++ ] \ ++ [list \ ++ "Build copyreloc-main with PIE without -fPIE (1)" \ ++ "tmpdir/copyreloc-main.o tmpdir/copyreloc-lib.so -pie" \ ++ "" \ ++ { dummy.s } \ + {{readelf {-Wr} copyreloc-main1.rd}} \ + "copyreloc-main" \ + ] \ + [list \ + "Build copyreloc-main with PIE without -fPIE (2)" \ +- "tmpdir/copyreloc-lib.so -pie" \ ++ "tmpdir/copyreloc-main.o tmpdir/copyreloc-lib.so -pie" \ + "" \ +- { copyreloc-main.S } \ ++ { dummy.s } \ + {{readelf {-Wr} copyreloc-main2.rd}} \ + "copyreloc-main" \ + ] \ +@@ -479,26 +499,33 @@ if { [isnative] && [which $CC] != 0 } { + "pr17689now.so" \ + ] \ + [list \ +- "Build pr17689 with PIE without -fPIE" \ +- "tmpdir/pr17689.so -pie" \ ++ "Build pr17689b.o" \ ++ "" \ + "" \ + { pr17689b.S } \ ++ {} \ ++ ] \ ++ [list \ ++ "Build pr17689 with PIE without -fPIE" \ ++ "tmpdir/pr17689b.o tmpdir/pr17689.so -pie" \ ++ "" \ ++ { dummy.s } \ + {{readelf {-Wr} pr17689.rd}} \ + "pr17689" \ + ] \ + [list \ + "Build pr17689 with PIE -z now without -fPIE" \ +- "tmpdir/pr17689.so -pie -Wl,-z,now" \ ++ "tmpdir/pr17689b.o tmpdir/pr17689.so -pie -Wl,-z,now" \ + "" \ +- { pr17689b.S } \ ++ { dummy.s } \ + {{readelf {-Wr} pr17689now.rd}} \ + "pr17689now" \ + ] \ + [list \ + "Build pr17827 with PIE without -fPIE" \ +- "tmpdir/pr17689.so -pie" \ ++ "-Wl,--as-needed tmpdir/pr17689b.o tmpdir/pr17689.so -pie" \ + "" \ +- { pr17689b.S } \ ++ { dummy.s } \ + {{readelf {-Wr} pr17827.rd}} \ + "pr17827" \ + ] \ +@@ -511,18 +538,26 @@ if { [isnative] && [which $CC] != 0 } { + "pr18900.so" \ + ] \ + [list \ +- "Build pr18900a" \ +- "tmpdir/pr18900.so" \ ++ "Build pr18900.o" \ ++ "-r -nostdlib" \ + "" \ + { pr18900b.c pr18900c.c } \ ++ "" \ ++ "pr18900.o" \ ++ ] \ ++ [list \ ++ "Build pr18900a" \ ++ "tmpdir/pr18900.o tmpdir/pr18900.so" \ ++ "" \ ++ { dummy.s } \ + {{readelf {-Wrd} pr18900a.rd}} \ + "pr18900a" \ + ] \ + [list \ + "Build pr18900b" \ +- "tmpdir/pr18900.so" \ ++ "-Wl,--as-needed tmpdir/pr18900.o tmpdir/pr18900.so" \ + "" \ +- { pr18900b.c pr18900c.c } \ ++ { dummy.s } \ + {{readelf {-Wrd} pr18900b.rd}} \ + "pr18900b" \ + ] \ +@@ -543,10 +578,18 @@ if { [isnative] && [which $CC] != 0 } { + "gotpcrel1d.so" \ + ] \ + [list \ +- "Build gotpcrel1" \ +- "tmpdir/gotpcrel1d.so" \ ++ "Build libgotpcrel1.a" \ ++ "" \ + "" \ { gotpcrel1a.S gotpcrel1b.c gotpcrel1c.c } \ ++ "" \ ++ "libgotpcrel1.a" \ ++ ] \ ++ [list \ ++ "Build gotpcrel1" \ ++ "-Wl,--as-needed tmpdir/gotpcrel1a.o tmpdir/gotpcrel1b.o tmpdir/gotpcrel1c.o tmpdir/gotpcrel1d.so" \ ++ "-Wa,-mrelax-relocations=yes" \ ++ { dummy.s } \ {{objdump {-dw} gotpcrel1.dd}} \ "gotpcrel1" \ + ] \ +@@ -590,33 +633,33 @@ if { [isnative] && [which $CC] != 0 } { + ] \ + [list \ + "Run copyreloc-main with PIE without -fPIE" \ +- "tmpdir/copyreloc-lib.so -pie" \ ++ "--as-needed tmpdir/copyreloc-main.o tmpdir/copyreloc-lib.so -pie" \ + "" \ +- { copyreloc-main.S } \ ++ { dummy.s } \ + "copyreloc-main" \ + "copyreloc-main.out" \ + ] \ + [list \ + "Run pr17689 with PIE without -fPIE" \ +- "tmpdir/pr17689.so -pie" \ ++ "tmpdir/pr17689b.o tmpdir/pr17689.so -pie" \ + "" \ +- { pr17689b.S } \ ++ { dummy.s } \ + "pr17689" \ + "pr17689.out" \ + ] \ + [list \ + "Run pr17689 with PIE -z now without -fPIE" \ +- "tmpdir/pr17689.so -pie -z now" \ ++ "--as-needed tmpdir/pr17689b.o tmpdir/pr17689.so -pie -z now" \ + "" \ +- { pr17689b.S } \ ++ { dummy.s } \ + "pr17689now" \ + "pr17689.out" \ + ] \ + [list \ + "Run pr18900" \ +- "tmpdir/pr18900.so" \ ++ "tmpdir/pr18900.o tmpdir/pr18900.so" \ + "" \ +- { pr18900b.c pr18900c.c } \ ++ { dummy.s } \ + "pr18900" \ + "pr18900.out" \ + ] \ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog -index 726335d..e7f539a 100644 +index 726335d..b146bd3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog -@@ -1,3 +1,24 @@ +@@ -1,3 +1,41 @@ ++2016-06-03 Peter Bergner ++ ++ Backport from master ++ 2016-06-03 Peter Bergner ++ ++ PR binutils/20196 ++ * ppc-opc.c (powerpc_opcodes ): Enable ++ opcodes for E6500. ++ ++2016-06-01 Peter Bergner ++ ++ Backport from master ++ 2016-05-26 Peter Bergner ++ ++ * ppc-opc.c (CY): New define. Document it. ++ (powerpc_opcodes) : New mnemonics. ++ +2016-02-26 Alan Modra + + Apply from master. @@ -6174,7 +8430,7 @@ index 726335d..e7f539a 100644 2016-01-25 Tristan Gingold * configure: Regenerate. -@@ -810,7 +831,7 @@ +@@ -810,7 +848,7 @@ 2015-05-11 H.J. Lu @@ -6292,10 +8548,20 @@ index 1b4c51a..3712b59 100644 } if (address_mode != mode_64bit diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c -index e8c92f6..9b25b60 100644 +index e8c92f6..b6cbbbc 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c -@@ -1434,7 +1434,7 @@ insert_fxm (unsigned long insn, +@@ -807,7 +807,9 @@ const struct powerpc_operand powerpc_operands[] = + #define X_R A_L + { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, + ++ /* The RMC or CY field in a Z23 form instruction. */ + #define RMC A_L + 1 ++#define CY RMC + { 0x3, 9, NULL, NULL, 0 }, + + #define R RMC + 1 +@@ -1434,7 +1436,7 @@ insert_fxm (unsigned long insn, /* A value of -1 means we used the one operand form of mfcr which is valid. */ if (value != -1) @@ -6304,7 +8570,15 @@ index e8c92f6..9b25b60 100644 value = 0; } -@@ -4742,8 +4742,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { +@@ -3137,6 +3139,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, + {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, + {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, ++{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}}, + {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, + {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, + {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +@@ -4742,8 +4745,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}}, {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}}, @@ -6314,3 +8588,58 @@ index e8c92f6..9b25b60 100644 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE, {RT, FXM}}, {"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, +@@ -4814,7 +4816,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}}, + {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}}, + +-{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, ++{"lbarx", X(31,52), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, + + {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}}, + +@@ -4894,7 +4896,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}}, + {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}}, + +-{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, ++{"lharx", X(31,116), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, + + {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, + +@@ -4970,6 +4972,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}}, + {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + ++{"addex", ZRC(31,170,0), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}}, ++{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}}, ++ + {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, PPCNONE, {RB}}, + {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, + +@@ -5497,6 +5502,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { + + {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, + ++{"lwzmx", X(31,437), X_MASK, POWER9, PPCNONE, {RT, RA0, RB}}, ++ + {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, + + {"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}}, +@@ -5939,7 +5946,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}}, + {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}}, + +-{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, ++{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}}, + + {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, + +@@ -5971,7 +5978,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { + {"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}}, + {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, + +-{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, ++{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}}, + + {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, + diff --git a/binutils.changes b/binutils.changes index c8f5ad9..e6c42b8 100644 --- a/binutils.changes +++ b/binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-aarch64-binutils.changes b/cross-aarch64-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-aarch64-binutils.changes +++ b/cross-aarch64-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-arm-binutils.changes b/cross-arm-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-arm-binutils.changes +++ b/cross-arm-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-avr-binutils.changes b/cross-avr-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-avr-binutils.changes +++ b/cross-avr-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-epiphany-binutils.changes b/cross-epiphany-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-epiphany-binutils.changes +++ b/cross-epiphany-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-hppa-binutils.changes b/cross-hppa-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-hppa-binutils.changes +++ b/cross-hppa-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-hppa64-binutils.changes b/cross-hppa64-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-hppa64-binutils.changes +++ b/cross-hppa64-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-i386-binutils.changes b/cross-i386-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-i386-binutils.changes +++ b/cross-i386-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-ia64-binutils.changes b/cross-ia64-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-ia64-binutils.changes +++ b/cross-ia64-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-m68k-binutils.changes b/cross-m68k-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-m68k-binutils.changes +++ b/cross-m68k-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-mips-binutils.changes b/cross-mips-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-mips-binutils.changes +++ b/cross-mips-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-ppc-binutils.changes b/cross-ppc-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-ppc-binutils.changes +++ b/cross-ppc-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-ppc64-binutils.changes b/cross-ppc64-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-ppc64-binutils.changes +++ b/cross-ppc64-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-ppc64le-binutils.changes b/cross-ppc64le-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-ppc64le-binutils.changes +++ b/cross-ppc64le-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-rx-binutils.changes b/cross-rx-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-rx-binutils.changes +++ b/cross-rx-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-s390-binutils.changes b/cross-s390-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-s390-binutils.changes +++ b/cross-s390-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-s390x-binutils.changes b/cross-s390x-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-s390x-binutils.changes +++ b/cross-s390x-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-sparc-binutils.changes b/cross-sparc-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-sparc-binutils.changes +++ b/cross-sparc-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-sparc64-binutils.changes b/cross-sparc64-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-sparc64-binutils.changes +++ b/cross-sparc64-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-spu-binutils.changes b/cross-spu-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-spu-binutils.changes +++ b/cross-spu-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com diff --git a/cross-x86_64-binutils.changes b/cross-x86_64-binutils.changes index c8f5ad9..e6c42b8 100644 --- a/cross-x86_64-binutils.changes +++ b/cross-x86_64-binutils.changes @@ -1,3 +1,8 @@ +------------------------------------------------------------------- +Mon Jun 13 12:35:51 UTC 2016 - rguenther@suse.com + +- Update binutils-2.26-branch.diff. + ------------------------------------------------------------------- Fri Mar 18 07:57:51 UTC 2016 - rguenther@suse.com