2008-12-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/7036
	* elfxx-ia64.c (elfNN_ia64_relax_section): Assume linker will
	always insert 32byte between the .plt and .text sections after
	the the first relaxation pass.

--- bfd/elfxx-ia64.c.relax	2008-11-29 12:08:04.000000000 -0800
+++ bfd/elfxx-ia64.c	2008-12-01 13:57:01.000000000 -0800
@@ -994,8 +994,20 @@ elfNN_ia64_relax_section (bfd *abfd, ase
 		     + sec->output_offset
 		     + roff) & (bfd_vma) -4;
 
+	  /* The .plt section is aligned at 32byte and the .text section
+	     is aligned at 64byte. The .text section is right after the
+	     .plt section.  After the first relaxation pass, linker may
+	     increase the gap between the .plt and .text sections up
+	     to 32byte.  We assume linker will always insert 32byte
+	     between the .plt and .text sections after the the first
+	     relaxation pass.  */
+	  if (tsec == ia64_info->plt_sec)
+	    offset = -0x1000000 + 32;
+	  else
+	    offset = -0x1000000;
+
 	  /* If the branch is in range, no need to do anything.  */
-	  if ((bfd_signed_vma) (symaddr - reladdr) >= -0x1000000
+	  if ((bfd_signed_vma) (symaddr - reladdr) >= offset 
 	      && (bfd_signed_vma) (symaddr - reladdr) <= 0x0FFFFF0)
 	    {
 	      /* If the 60-bit branch is in 21-bit range, optimize it. */