forked from pool/binutils
f32da6f20f
* new .base64 pseudo-op, allowing base64 encoded data as strings * Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF (APX_F now fully supported) * x86 Intel syntax now warns about more mnemonic suffixes * macros and .irp/.irpc/.rept bodies can use \+ to get at number of times the macro/body was executed * aarch64: support 'armv9.5-a' for -march, add support for LUT and LUT2 * s390: base register operand in D(X,B) and D(L,B) can now be omitted (ala 'D(X,)'); warn when register type doesn't match operand type (use option 'warn-regtype-mismatch=[strict|relaxed|no]' to adjust) * riscv: support various extensions: Zacas, Zcmp, Zfbfmin, Zvfbfmin, Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw, XSfCease, all at version 1.0; remove support for assembly of privileged spec 1.9.1 (linking support remains) * arm: remove support for some old co-processors: Maverick and FPA * mips: '--trap' now causes either trap or breakpoint instructions to be emitted as per current ISA, instead of always using trap insn and failing when current ISA was incompatible with that * LoongArch: accept .option pseudo-op for fine-grained control of assembly code options; add support for DT_RELR * readelf: now displays RELR relocations in full detail; add -j/--display-section to show just those section(s) content according to their type * objdump/readelf now dump also .eh_frame_hdr (when present) when dumping .eh_frame * gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake processors; add minimal support for riscv * linker: OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=471
65 lines
2.4 KiB
Diff
65 lines
2.4 KiB
Diff
From af514e5f6d1d0233a251a3ae17f7cb8d9ba8e36b Mon Sep 17 00:00:00 2001
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From: Nelson Chu <nelson@rivosinc.com>
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Date: Mon, 29 Jan 2024 21:17:41 +0800
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Subject: [PATCH] RISC-V: Don't generate branch/jump relocation if symbol is
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local when no-relax.
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Refer to commit, dff565fcca8137954d6ad571ef39f6aec5c0429c. Theoretically,
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assembler don't need to generate the pc-relative relocation and the refered
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local .L symbol when relaxation is disabled. The above commit improved the
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pcrel_hi/pcrel_lo relocations, and this commit improves branch and jump
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relocations.
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Passed the gcc/binutils regressions of riscv-gnu-toolchain.
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gas/
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* config/tc-riscv.c (md_apply_fix): Raise fixP->fx_done for all
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branch and jump relocations when -mno-relax.
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---
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gas/config/tc-riscv.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
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index a4161420128..cbead954f09 100644
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--- a/gas/config/tc-riscv.c
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+++ b/gas/config/tc-riscv.c
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@@ -4390,6 +4390,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
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bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
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bfd_vma delta = target - md_pcrel_from (fixP);
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bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf);
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+ if (!riscv_opts.relax && S_IS_LOCAL (fixP->fx_addsy))
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+ fixP->fx_done = 1;
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}
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break;
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@@ -4400,6 +4402,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
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bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
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bfd_vma delta = target - md_pcrel_from (fixP);
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bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf);
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+ if (!riscv_opts.relax && S_IS_LOCAL (fixP->fx_addsy))
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+ fixP->fx_done = 1;
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}
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break;
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@@ -4410,6 +4414,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
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bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
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bfd_vma delta = target - md_pcrel_from (fixP);
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bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf);
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+ if (!riscv_opts.relax && S_IS_LOCAL (fixP->fx_addsy))
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+ fixP->fx_done = 1;
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}
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break;
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@@ -4420,6 +4426,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
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bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
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bfd_vma delta = target - md_pcrel_from (fixP);
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bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf);
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+ if (!riscv_opts.relax && S_IS_LOCAL (fixP->fx_addsy))
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+ fixP->fx_done = 1;
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}
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break;
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--
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2.43.2
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