--- sysdeps/powerpc/fpu/fenv_libc.h.~1.5.~	2008-11-17 10:44:10.000000000 +0100
+++ sysdeps/powerpc/fpu/fenv_libc.h	2009-01-22 14:23:37.000000000 +0100
@@ -39,7 +39,7 @@ libm_hidden_proto (__fe_nomask_env)
 	do { \
 	  double d = (env); \
 	  if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
-	    asm volatile ("mtfsf 0xff,%0,1,0" : : "f" (d)); \
+	    asm volatile (".machine push; .machine power6; mtfsf 0xff,%0,1,0; .machine pop" : : "f" (d)); \
 	  else \
 	    asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
 	} while(0)
@@ -53,7 +53,7 @@ libm_hidden_proto (__fe_nomask_env)
 #define relax_fenv_state() \
 	do { \
 	   if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
-	       asm ("mtfsfi 7,0,1"); \
+	       asm (".machine push; .machine power6; mtfsfi 7,0,1; .machine pop"); \
 	   asm ("mtfsfi 7,0"); \
 	} while(0)
 
--- sysdeps/powerpc/fpu/tst-setcontext-fpscr.c.~1.1.~	2008-11-17 02:34:02.000000000 +0100
+++ sysdeps/powerpc/fpu/tst-setcontext-fpscr.c	2009-01-22 14:24:33.000000000 +0100
@@ -109,7 +109,7 @@ typedef unsigned int si_fpscr_t __attrib
     tmp __attribute__ ((__aligned__(8)));				     \
   tmp.fpscr = __fpscr;							     \
   /* Set the entire 64-bit FPSCR.  */					     \
-  __asm__ ("lfd%U0 0,%0; mtfsf 255,0,1,0" : : "m" (tmp.d) : "fr0");	     \
+  __asm__ ("lfd%U0 0,%0; .machine push; .machine power6; mtfsf 255,0,1,0; .machine pop" : : "m" (tmp.d) : "fr0");	     \
 }
 
 # define _GET_SI_FPSCR(__fpscr) ({					     \
--- sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S.~1.4.~	2008-11-17 10:44:18.000000000 +0100
+++ sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S	2009-01-22 15:42:24.000000000 +0100
@@ -202,13 +202,19 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	lfd	fp0,_UC_FREGS+(0*8)(r31)
 # ifdef _ARCH_PWR6
 	/* Use the extended four-operand version of the mtfsf insn.  */
+	.machine push
+	.machine power6
 	mtfsf  0xff,fp31,1,0
+	.machine pop
 # else
 	/* Availability of DFP indicates a 64-bit FPSCR.  */
 	andi.	r6,r7,PPC_FEATURE_HAS_DFP
 	beq	7f
 	/* Use the extended four-operand version of the mtfsf insn.  */
+	.machine push
+	.machine power6
 	mtfsf	0xff,fp31,1,0
+	.machine pop
 	b	8f
 	/* Continue to operate on the FPSCR as if it were 32-bits.  */
 7:	mtfsf	0xff,fp31
--- sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S.~1.3.~	2008-11-17 10:44:18.000000000 +0100
+++ sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S	2009-01-22 15:42:37.000000000 +0100
@@ -428,13 +428,19 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	lfd	fp0,_UC_FREGS+(0*8)(r31)
 # ifdef _ARCH_PWR6
 	/* Use the extended four-operand version of the mtfsf insn.  */
+	.machine push
+	.machine power6
 	mtfsf  0xff,fp31,1,0
+	.machine pop
 # else
 	/* Availability of DFP indicates a 64-bit FPSCR.  */
 	andi.	r6,r7,PPC_FEATURE_HAS_DFP
 	beq	7f
 	/* Use the extended four-operand version of the mtfsf insn.  */
+	.machine push
+	.machine power6
 	mtfsf	0xff,fp31,1,0
+	.machine pop
 	b	8f
 	/* Continue to operate on the FPSCR as if it were 32-bits.  */
 7:	mtfsf	0xff,fp31
--- sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S.~1.14.~	2008-11-17 10:44:18.000000000 +0100
+++ sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S	2009-01-22 15:43:05.000000000 +0100
@@ -84,13 +84,19 @@ ENTRY(__novec_setcontext)
 
 # ifdef _ARCH_PWR6
   /* Use the extended four-operand version of the mtfsf insn.  */
+  .machine push
+  .machine power6
   mtfsf  0xff,fp0,1,0
+  .machine pop
 # else
   /* Availability of DFP indicates a 64-bit FPSCR.  */
   andi.  r6,r5,PPC_FEATURE_HAS_DFP
   beq    5f
   /* Use the extended four-operand version of the mtfsf insn.  */
+  .machine push
+  .machine power6
   mtfsf  0xff,fp0,1,0
+  .machine pop
   b      6f
   /* Continue to operate on the FPSCR as if it were 32-bits.  */
 5:
@@ -372,13 +378,19 @@ L(has_no_vec):
 
 # ifdef _ARCH_PWR6
   /* Use the extended four-operand version of the mtfsf insn.  */
+  .machine push
+  .machine power6
   mtfsf  0xff,fp0,1,0
+  .machine pop
 # else
   /* Availability of DFP indicates a 64-bit FPSCR.  */
   andi.  r6,r5,PPC_FEATURE_HAS_DFP
   beq    7f
   /* Use the extended four-operand version of the mtfsf insn.  */
+  .machine push
+  .machine power6
   mtfsf  0xff,fp0,1,0
+  .machine pop
   b      8f
   /* Continue to operate on the FPSCR as if it were 32-bits.  */
 7:
--- sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S.~1.17.~	2008-11-17 10:44:18.000000000 +0100
+++ sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S	2009-01-22 15:43:26.000000000 +0100
@@ -178,13 +178,19 @@ ENTRY(__novec_swapcontext)
   lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
 # ifdef _ARCH_PWR6
   /* Use the extended four-operand version of the mtfsf insn.  */
+  .machine push
+  .machine power6
   mtfsf  0xff,fp0,1,0
+  .machine pop
 # else
   /* Availability of DFP indicates a 64-bit FPSCR.  */
   andi.  r6,r8,PPC_FEATURE_HAS_DFP
   beq    5f
   /* Use the extended four-operand version of the mtfsf insn.  */
+  .machine push
+  .machine power6
   mtfsf  0xff,fp0,1,0
+  .machine pop
   b      6f
   /* Continue to operate on the FPSCR as if it were 32-bits.  */
 5:
@@ -670,13 +676,19 @@ L(has_no_vec2):
   lfd  fp30,(SIGCONTEXT_FP_REGS+(PT_R30*8))(r31)
 # ifdef _ARCH_PWR6
   /* Use the extended four-operand version of the mtfsf insn.  */
+  .machine push
+  .machine power6
   mtfsf  0xff,fp0,1,0
+  .machine pop
 # else
   /* Availability of DFP indicates a 64-bit FPSCR.  */
   andi.  r6,r8,PPC_FEATURE_HAS_DFP
   beq    7f
   /* Use the extended four-operand version of the mtfsf insn.  */
+  .machine push
+  .machine power6
   mtfsf  0xff,fp0,1,0
+  .machine pop
   b      8f
   /* Continue to operate on the FPSCR as if it were 32-bits.  */
 7: