forked from pool/openssl-3
Pedro Monreal Gonzalez
6bc57d937f
* SHA-1 is not allowed anymore in FIPS 186-5 for signature
verification operations. After 12/31/2030, NIST will disallow
SHA-1 for all of its usages.
* Add openssl-3-FIPS-Deny-SHA-1-sigver-in-FIPS-provider.patch
- FIPS: RSA keygen PCT requirements.
* Skip the rsa_keygen_pairwise_test() PCT in rsa_keygen() as the
self-test requirements are covered by do_rsa_pct() for both
RSA-OAEP and RSA signatures [bsc#1221760]
* Enforce error state if rsa_keygen PCT is run and fails [bsc#1221753]
* Add openssl-3-FIPS-PCT_rsa_keygen.patch
- FIPS: Check that the fips provider is available before setting
it as the default provider in FIPS mode. [bsc#1220523]
* Rebase openssl-Force-FIPS.patch
- FIPS: Port openssl to use jitterentropy [bsc#1220523]
* Set the module in error state if the jitter RNG fails either on
initialization or entropy gathering because health tests failed.
* Add jitterentropy as a seeding source output also in crypto/info.c
* Move the jitter entropy collector and the associated lock out
of the header file to avoid redefinitions.
* Add the fips_local.cnf symlink to the spec file. This simlink
points to the openssl_fips.config file that is provided by the
crypto-policies package.
* Rebase openssl-3-jitterentropy-3.4.0.patch
* Rebase openssl-FIPS-enforce-EMS-support.patch
- FIPS: Block non-Approved Elliptic Curves [bsc#1221786]
OBS-URL: https://build.opensuse.org/package/show/security:tls/openssl-3?expand=0&rev=110
110 lines
2.8 KiB
Diff
110 lines
2.8 KiB
Diff
From 050d26383d4e264966fb83428e72d5d48f402d35 Mon Sep 17 00:00:00 2001
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From: Rohan McLure <rmclure@linux.ibm.com>
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Date: Thu, 4 Jan 2024 10:25:50 +0100
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Subject: [PATCH] poly1305-ppc.pl: Fix vector register clobbering
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Fixes CVE-2023-6129
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The POLY1305 MAC (message authentication code) implementation in OpenSSL for
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PowerPC CPUs saves the the contents of vector registers in different order
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than they are restored. Thus the contents of some of these vector registers
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is corrupted when returning to the caller. The vulnerable code is used only
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on newer PowerPC processors supporting the PowerISA 2.07 instructions.
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Reviewed-by: Matt Caswell <matt@openssl.org>
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Reviewed-by: Richard Levitte <levitte@openssl.org>
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Reviewed-by: Tomas Mraz <tomas@openssl.org>
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(Merged from https://github.com/openssl/openssl/pull/23200)
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(cherry picked from commit 8d847a3ffd4f0b17ee33962cf69c36224925b34f)
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---
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crypto/poly1305/asm/poly1305-ppc.pl | 42 ++++++++++++++---------------
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1 file changed, 21 insertions(+), 21 deletions(-)
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diff --git a/crypto/poly1305/asm/poly1305-ppc.pl b/crypto/poly1305/asm/poly1305-ppc.pl
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index 9f86134d923fb..2e601bb9c24be 100755
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--- a/crypto/poly1305/asm/poly1305-ppc.pl
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+++ b/crypto/poly1305/asm/poly1305-ppc.pl
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@@ -744,7 +744,7 @@
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my $LOCALS= 6*$SIZE_T;
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my $VSXFRAME = $LOCALS + 6*$SIZE_T;
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$VSXFRAME += 128; # local variables
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- $VSXFRAME += 13*16; # v20-v31 offload
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+ $VSXFRAME += 12*16; # v20-v31 offload
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my $BIG_ENDIAN = ($flavour !~ /le/) ? 4 : 0;
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@@ -919,12 +919,12 @@
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addi r11,r11,32
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stvx v22,r10,$sp
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addi r10,r10,32
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- stvx v23,r10,$sp
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- addi r10,r10,32
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- stvx v24,r11,$sp
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+ stvx v23,r11,$sp
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addi r11,r11,32
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- stvx v25,r10,$sp
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+ stvx v24,r10,$sp
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addi r10,r10,32
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+ stvx v25,r11,$sp
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+ addi r11,r11,32
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stvx v26,r10,$sp
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addi r10,r10,32
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stvx v27,r11,$sp
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@@ -1153,12 +1153,12 @@
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addi r11,r11,32
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stvx v22,r10,$sp
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addi r10,r10,32
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- stvx v23,r10,$sp
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- addi r10,r10,32
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- stvx v24,r11,$sp
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+ stvx v23,r11,$sp
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addi r11,r11,32
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- stvx v25,r10,$sp
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+ stvx v24,r10,$sp
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addi r10,r10,32
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+ stvx v25,r11,$sp
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+ addi r11,r11,32
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stvx v26,r10,$sp
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addi r10,r10,32
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stvx v27,r11,$sp
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@@ -1899,26 +1899,26 @@
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mtspr 256,r12 # restore vrsave
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lvx v20,r10,$sp
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addi r10,r10,32
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- lvx v21,r10,$sp
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- addi r10,r10,32
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- lvx v22,r11,$sp
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+ lvx v21,r11,$sp
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addi r11,r11,32
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- lvx v23,r10,$sp
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+ lvx v22,r10,$sp
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addi r10,r10,32
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- lvx v24,r11,$sp
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+ lvx v23,r11,$sp
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addi r11,r11,32
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- lvx v25,r10,$sp
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+ lvx v24,r10,$sp
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addi r10,r10,32
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- lvx v26,r11,$sp
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+ lvx v25,r11,$sp
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addi r11,r11,32
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- lvx v27,r10,$sp
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+ lvx v26,r10,$sp
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addi r10,r10,32
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- lvx v28,r11,$sp
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+ lvx v27,r11,$sp
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addi r11,r11,32
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- lvx v29,r10,$sp
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+ lvx v28,r10,$sp
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addi r10,r10,32
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- lvx v30,r11,$sp
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- lvx v31,r10,$sp
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+ lvx v29,r11,$sp
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+ addi r11,r11,32
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+ lvx v30,r10,$sp
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+ lvx v31,r11,$sp
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$POP r27,`$VSXFRAME-$SIZE_T*5`($sp)
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$POP r28,`$VSXFRAME-$SIZE_T*4`($sp)
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$POP r29,`$VSXFRAME-$SIZE_T*3`($sp)
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