diff --git a/cpuid-20230614.src.tar.gz b/cpuid-20230614.src.tar.gz deleted file mode 100644 index 1effc97..0000000 --- a/cpuid-20230614.src.tar.gz +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:b1c83045efc26076307751e0662d580277f5f9bf89cf027231a7812003c3a4e8 -size 149777 diff --git a/cpuid-20240716.src.tar.gz b/cpuid-20240716.src.tar.gz new file mode 100644 index 0000000..0a53a6e --- /dev/null +++ b/cpuid-20240716.src.tar.gz @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6fc4d666a601296fed005ce8277f2c65d1f56d717c4efb6527ad4112c6573ee4 +size 155562 diff --git a/cpuid.changes b/cpuid.changes index c5e9f9c..7e77c8c 100644 --- a/cpuid.changes +++ b/cpuid.changes @@ -1,3 +1,171 @@ +------------------------------------------------------------------- +Mon Aug 5 16:05:55 UTC 2024 - Valentin Lefebvre + +- Update to release 20240716 + * cpuid.c: For AMD Zen CPUs, overhauled uarch & synth decoding to + determine the CPU model from only the extended model & high bit of the + model field. Also, determine the stepping (revision) mechanically + from the low-order 3 bits of the model and the stepping number. + This should correctly identify retail Zen 5 Ryzen's. This also + corrects some stepping bugs from the Zen 1 era. +- Update to release 20240709 + * cpuid.c: Added 6/eax IA32_HWP_CTL MSR supported. + * cpuid.c: Added 7/2/edx MONITOR perf unaffected by tbl overflow. + * cpuid.c: Added synth decoding for Hygon Dhyana B1 & C2. Still no + information on a uarch name for these, so decode_uarch_hygon() remains + silent for them. + * cpuid.c: Added uarch synth decoding for (0,6),(5,5),11 Cooper Lake. + The synth decoding was already present. Its absence from + decode_uarch_intel was just an oversight. + * cpuid.c: Fixed division-by-zero error in decode_mp_synth Intel leaf + 1/4 (zero fallback). This is meant for old, incomplete cpuid -r + dumps, but even for hand-crafted dumps, determining 0 cores and then + dividing by that 0 is unacceptable. +- Update to release 20240409 + * cpuid.c: Added 0x8000000a/edx PMC virtualization. + * cpuid.c: Added 0x8000000a/edx idle HLT intercept. + * cpuid.c: Added 0x8000001f/eax PMC virtual support for SEV-ES/SNP. + * cpuid.c: Added 0x8000001f/eax mention of SEV-SNP to existing fields. + * cpuid.c: Added 0x8000001f/eax RMPREAD instruction. + * cpuid.c: Added 0x8000001f/eax secure AVIC support. + * cpuid.c: Added 0x8000001f/eax allowed SEV features support. + * cpuid.c: Added 0x8000001f/eax write to hypervisor in-used allowed. + * cpuid.c: Added 0x8000001f/eax IBPB on entry support. + * cpuid.c: Added Siena to (10,15),(10,x) synth decoding, based on 58268 + Arch Overview. + * cpuid.man: Added 58268: AMD EPYC 8004 Series Architecture Overview. + * cpuid.c: Added preliminary (10,15),(7,12) Hawk Point synth decoding. + * cpuid.c: Fixed spelling: EPGR->EGPR (extended GPR's). +- Update to release 20240330 + * cpuid.c: Added 5/ecx monitorless MWAIT. + * cpuid.c: Added 7/1/edx user-timer events. + * cpuid.c: Added 7/1/edx AVX10 instructions. + * cpuid.c: Added 7/1/edx APX advanced performance extensions. + * cpuid.c: Added 7/1/edx MWAIT instruction (overrides 1/ecx[3]). + * cpuid.c: Added Intel-specific print_instr_synth_intel to determine + presence of MWAIT from 1/ecx and/or 7/1/edx. + * cpuid.c: Updated 12/n/ecx section property values 1 & 3. + * cpuid.c: Added 14/0/ebx PTTT processor trace trigger tracing. + * cpuid.c: Added 14/1/eax number of IA32_RTIT_TRIGGERx_CFG MSRs, + including D4_IMAGES decoding. + * cpuid.c: Added 14/1/ecx flags. + * cpuid.c: Added MINUS24_IMAGES decoding for 0xf/1/eax QoS monitoring + counter size. + * cpuid.c: Added 0x23/1 sub-header: Architecture Performance Monitoring + Extended Counters Supported Bitmaps (0x23/1), and simplified fields. + * cpuid.c: Added 0x23/2 sub-header: Architecture Performance Monitoring + Extended Auto Counter Reload (ACR) Bitmaps (0x23/2), expanded on + existing field descriptions, and added "can cause reloads" fields. + * cpuid.c: Added 0x24 leaf: Converged Vector ISA. + * cpuid.c: Added to print_d_n: new XSAVE area: 19 for APX EPGR + (extended general purpose registers). + * cpuid.man: Added new Intel 355828 (APX) doc. + * cpuid.c: Added uarch decoding for (11,15),(1,0), which is mentioned + with (11,15),(0,0) in the title of 58088 AMD 1Ah Models 00h-0Fh and + Models 10h-1Fh ACPI v6.5 Porting Guide. + * cpuid.c: Expanded br.xeon test to include brands with "XEON", and + br.scalable to include "BRONZE", "PLATINUM", etc. (all caps), based on + Emerald Rapids (engr?) sample. I don't know if this is a change Intel + will use moving forward, or a quirk of engr samples, but checking for + it is harmless enough. +- Update to release 20240324 + * cpuid.c: Updated synth decoding for (0,6),(12,15),2 Emerald Rapids + A1/R1. + * cpuid.man: Added new Intel docs. + * cpuid.c: In do_real(), for the 0x1b leaf, add a sanity check to avoid + infinite recursion if a hypervisor never reports invalid (0) on any + subleaf. The sanity check checks for a subleaf identical to its + predecessor, which is not reasonable. + * cpuid.c: Added synth & uarch decoding for (0,6),(13,13) Clearwater + Forest. + * cpuid.c: Updated (0,6),(8,12),1 to include stepping B0, from ILPMDF* + * cpuid.c: Updated (0,6),(11,15),5 to Raptor Lake stepping H0, based on + preponderance of evidence. + * cpuid.c: Added synth decoding for (0,6),(10,10) Core Ultra CPUs. + * cpuid.c: Updated (0,6),(11,7) to include Core i*-14000. Some CPUs + having this branding, and it's not clear what's different from the + Core i*-13000 versions. The steppings don't seem to matter. + Inspection suggests maybe CET_SSS. + * cpuid.c: Corrected synth decoding for (10,15),(1,8) Storm Peak: Ryzen + Threadripper 7000. + * cpuid.c: Added synth decoding for (10,15),(7,5),2 AMD Ryzen Phoenix F2. + * cpuid.c: Added very preliminary uarch decoding for (10,15),(6,0) and + (10,15),(7,0), both Zen 5. + * cpuid.c: Changed preliminary synth decoding for (0,6),(11,5) to Arrow + Lake, based on Intel SDE 9.33.0. + * cpuid.c: Added synth decoding for (0,6),(8,13),0 Tiger Lake-H P0 + stepping. + * cpuid.c: Added synth decoding for (0,6),(11,13),0 Lunar Lake A0 + stepping. + * cpuid.c: Changed uarch decoding for (0,6),(13,13) to Darkmont, the + presumed uarch for Clearwater Forest. + * cpuid.c: Added 12/1/eax AEX attribute enabled, as described by Scott + Raynor, Intel. + * cpuid.c: Added 7/1/eax NMI-source reporting. + * cpuid.c: Added 7/1/eax INVD prevention after BIOS done. + * cpuid.c: Renamed 7/1/ebx PKNDKB instruction. + * cpuid.c: Added 7/1/edx URDMSR, UWRMSR instructions. + * cpuid.c: Added 0xa/ebx additional events. + * cpuid.c: Added 0xf/1/eax non-CPU agent features. + * cpuid.c: For 0xf/0/edx supports L3 cache monitoring, removed + redundant "QoS". + * cpuid.c: Renamed print_10_n_{eax,ecx} -> print_10_12_{eax,ecx}. + * cpuid.c: Added 0x10/0/ebx cache bandwidth allocation supported. + * cpuid.c: Replaced 0x10/{1,2}/ecx: non-CPU agent support. + * cpuid.c: Renamed 0x10/{1,2}/ecx: non-contiguous bitmask supported. + * cpuid.c: Added 0x10/5 Cache Bandwidth Allocation decoding. + * cpuid.c: Renamed 0x23/0/ebx IA32_PERFEVTSELx EQ bit supported. + * cpuid.c: Added 0x23/2 ACR counters bitmaps. + * cpuid.c: Corrected synth decoding for (10,15),(10,x) to EPYC (4th Gen) + (server CPUs), instead of Ryzen (desktop CPUs). + * cpuid.c: Added (0,6),(12,12) Panther Lake synth decoding from LX*, but + left out corresponding uarch decoding which is alls rumors currently: + maybe Panther Cove, Cougar Cove, or something else. + * cpuid.c: Added hypervisor+0xc ebx isolation type new value: TDX (3) + from LX*. + * cpuid.c: Added (11,5),(0,0) Zen 5 uarch from LX*. + * cpuid.c: To decode_uarch_intel, added (0,6),(11,12) & (0,6),(11,13) + Lion Cove & Skymont as uarch underpinning Lunar Lake. + * cpuid.c: Added 0x80000021/eax selective branch prediction barrier, + PRED_CMD[IBPB] flushes branch type preds. They appear to be only + synthetic flags provided for hypervisor guests! + * cpuid.c: Added 0x80000021/eax CPU not affected by SRSO flag, from LX*. + * cpuid.c: Added (10,15),(8&9,0) uarch & synth decoding for AMD Instinct + MI300, from LKML: https://lkml.org/lkml/2023/7/20/668 patches. + In the past, Instinct MI* described just the GPU, but they seem to be + conflating them into a product name here. + * cpuid.: Added prelim uarch decoding for (11,15),(2,0) & (11,15),(4,0), + both Zen 5, based on engr samples. No synth decoding yet, because it + isn't known yet. + * cpuid.c: Added prelim synth decoding for (0,6),(11,12) Lunar Lake from + Intel SDE 9.24.0 misc/cpuid/lnl/cpuid.def. No uarch decoding, because + Lunar Lake uarch name is not known yet. + * cpuid.c: Added prelim synth decoding for (0,6),(9,5) Sapphire Rapids + from Intel SDE 9.24.0 misc/cpuid/spr/cpuid.def. + * cpuid.c: Added synth decoding for (0,6),(11,7),0 Raptor Lake A0 + stepping, from Coreboot*. + * cpuid.c: Added 7/1/eax SHA512, SM3 & SM4 instructions. + * cpuid.c: Added 7/1/ebx TSE PBNDKB instruction. + * cpuid.c: Added 7/1/ebx AVX-VNNI-INT16 instructions. + * cpuid.c: Added 7/1/edx UIRET flexibly updates UIF. + * cpuid.c: Added 0x1b/2 TSE target. + * cpuid.c: Corrected sub-leaf walk of leaf 0x1b to stop immediately if + sub-leaf 0 is invalid. + * cpuid.c: Added (uarch synth) & (synth) decoding for (0,6),(12,5) + Arrow Lake based on Lion Cove & Skymont. + * cpuid.c: Added 0x80000008/ebx IBPB_RET. + * cpuid.c: Renamed 0x8000000a/edx extended LVT AVIC access changes. + * cpuid.c: Renamed 0x8000000a/edx guest VMCB addr check. + * cpuid.c: Added 0x8000000a/edx bus lock threshold. + * cpuid.c: Renamed several 0x80000020 leaves & fields. + * cpuid.c: Added 0x80000020/0/ebx assignable bandwidth monitoring + counters. + * cpuid.c: Added 0x80000020/0/ebx SDCI allocation enforcement + * cpuid.c: Added 0x80000020/5 PQoS Assignable Bandwidth Monitoring + Counters. + * cpuid.c: Added (synth) decoding for (0,6),(10,10),4 Meteor Lake-M C0 + stepping from Coreboot* + ------------------------------------------------------------------- Wed Jun 21 09:18:20 UTC 2023 - Valentin Lefebvre diff --git a/cpuid.spec b/cpuid.spec index 6bbda2e..b4caac9 100644 --- a/cpuid.spec +++ b/cpuid.spec @@ -1,7 +1,7 @@ # # spec file for package cpuid # -# Copyright (c) 2023 SUSE LLC +# Copyright (c) 2024 SUSE LLC # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,7 +17,7 @@ Name: cpuid -Version: 20230614 +Version: 20240716 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later