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target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig

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Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li
2023-03-09 15:13:26 +08:00
committed by Alistair Francis
parent f6b761bdbd
commit 9c33e08b2b
3 changed files with 18 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
target/riscv/cpu_helper.c
View File

@@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
uint64_t pending, uint8_t *iprio)
{
RISCVCPU *cpu = env_archcpu(env);
int irq, best_irq = RISCV_EXCP_NONE;
unsigned int prio, best_prio = UINT_MAX;
@@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
}
irq = ctz64(pending);
if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
riscv_cpu_cfg(env)->ext_ssaia)) {
return irq;
}
@@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
bool use_background = false;
hwaddr ppn;
RISCVCPU *cpu = env_archcpu(env);
int napot_bits = 0;
target_ulong napot_mask;
@@ -946,7 +945,7 @@ restart:
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
} else if (pbmte || cpu->cfg.ext_svnapot) {
} else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
} else {
ppn = pte >> PTE_PPN_SHIFT;
@@ -1043,7 +1042,7 @@ restart:
benefit. */
target_ulong vpn = addr >> PGSHIFT;
if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
napot_bits = ctzl(ppn) + 1;
if ((i != (levels - 1)) || (napot_bits != 4)) {
return TRANSLATE_FAIL;

40
target/riscv/csr.c
View File

@@ -89,9 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
RISCVCPU *cpu = env_archcpu(env);
if (cpu->cfg.ext_zve32f) {
if (riscv_cpu_cfg(env)->ext_zve32f) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -194,9 +192,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
static RISCVException sscofpmf(CPURISCVState *env, int csrno)
{
RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_sscofpmf) {
if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -311,9 +307,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
static RISCVException mstateen(CPURISCVState *env, int csrno)
{
RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_smstateen) {
if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -322,9 +316,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
{
RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_smstateen) {
if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -391,10 +383,9 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
static RISCVException sstc(CPURISCVState *env, int csrno)
{
RISCVCPU *cpu = env_archcpu(env);
bool hmode_check = false;
if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -1171,27 +1162,21 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
target_ulong *val)
{
RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.mvendorid;
*val = riscv_cpu_cfg(env)->mvendorid;
return RISCV_EXCP_NONE;
}
static RISCVException read_marchid(CPURISCVState *env, int csrno,
target_ulong *val)
{
RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.marchid;
*val = riscv_cpu_cfg(env)->marchid;
return RISCV_EXCP_NONE;
}
static RISCVException read_mimpid(CPURISCVState *env, int csrno,
target_ulong *val)
{
RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.mimpid;
*val = riscv_cpu_cfg(env)->mimpid;
return RISCV_EXCP_NONE;
}
@@ -1233,9 +1218,8 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
return (vm & 0xf) <=
satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
}
static RISCVException write_mstatus(CPURISCVState *env, int csrno,
@@ -1898,7 +1882,7 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
if (riscv_cpu_mxl(env) == MXL_RV64) {
@@ -1921,7 +1905,7 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_HADE : 0);

4
target/riscv/gdbstub.c
View File

@@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
{
uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
if (n < 32) {
int i;
int cnt = 0;
@@ -146,7 +146,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
{
uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
if (n < 32) {
int i;
for (i = 0; i < vlenb; i += 8) {