dfaggioli/qemu
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
112,667 Commits 59 Branches 1,031 Tags
c8b39c9b5b901b173fbbb0ec3f147e9694ece48c
Commit Graph

13136 Commits

Author SHA1 Message Date
Richard Henderson
0880d20b2e target/sparc: Move simple integer load/store to decodetree 
Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX,
STW, STB, STH, STD, STX.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
ebbbec9216 target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX 
Perform one atomic 16-byte operation.
The atomicity is required for the LDTXA instructions.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
c03a0fd15c target/sparc: Split out ldst functions with asi pre-computed 
As an intermediate step in decodetree conversion, create
new functions passing in DisasASI and not insn.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
a76779ee3b target/sparc: Drop ifdef around get_asi and friends 
Mark some of the functions as unused, temporarily.
Fix up some tl vs i64 issues revealed in the process.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
811cc0b0ce target/sparc: Split out resolve_asi 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
8f75b8a4eb target/sparc: Move DONE, RETRY to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
d382580031 target/sparc: Move FLUSH, SAVE, RESTORE to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
86b82fe021 target/sparc: Move JMPL, RETT, RETURN to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
d3c7e8ad74 target/sparc: Convert remaining v8 coproc insns to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
9c6ec5bcad target/sparc: Move POPC to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
fb4ed7aad4 target/sparc: Move MOVcc, MOVR to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
5fc546ee35 target/sparc: Move SLL, SRL, SRA to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
a9aba13dae target/sparc: Move TADD, TSUB, MULS to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
c26368532d target/sparc: Move UDIV, SDIV to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
4ee85ea94b target/sparc: Move UDIVX, SDIVX to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
dfebb950da target/sparc: Move SUBC to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
b5372650e2 target/sparc: Move UMUL, SMUL to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
22188d7da8 target/sparc: Move MULX to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
420a187d80 target/sparc: Move ADDC to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
428881deba target/sparc: Move basic arithmetic to decodetree 
Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
2da789ded5 target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver 
Use direct loads and stores to env instead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
577efa4557 target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr 
Use direct loads and stores to env instead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
cd6269f7c9 target/sparc: Remove cpu_wim 
Use direct loads and stores to env instead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
bb97f2f5d7 target/sparc: Move WRTBR, WRHPR to decodetree 
Implement htstate in the obvious way.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
9422278ef8 target/sparc: Move WRWIM, WRPR to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
25524734c6 target/sparc: Move WRPSR, SAVED, RESTORED to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
0faef01b39 target/sparc: Move WRASR to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
e8325dc02d target/sparc: Move RDTBR, FLUSHW to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
5d617bfba0 target/sparc: Move RDWIM, RDPR to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
668bb9b755 target/sparc: Move RDPSR, RDHPR to decodetree 
Implement htstate in the obvious way.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/847
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
af25071c1d target/sparc: Move RDASR, STBAR, MEMBAR to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
3037663616 target/sparc: Move Tcc to decodetree 
Use the new delay_exceptionv function in the implementation.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
6d2a076842 target/sparc: Move SETHI to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
9d4e2bc761 target/sparc: Pass DisasCompare to advance_jump_cond 
Fold the condition into the branch or movcond when possible.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:13 -07:00
Richard Henderson
6b3e4cc685 target/sparc: Merge gen_branch_[an] with only caller 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
d547193616 target/sparc: Merge gen_fcond with only caller 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
1ea9c62a5e target/sparc: Merge gen_cond with only caller 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
45196ea4f4 target/sparc: Move FBPfcc and FBfcc to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
ab9ffe988a target/sparc: Move BPr to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
276567aaf6 target/sparc: Move BPcc and Bicc to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
23ada1b16f target/sparc: Move CALL to decodetree 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
b1bc09ea6b target/sparc: Define AM_CHECK for sparc32 
Define as false, which allows some ifdef removal.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
878cc6773a target/sparc: Add decodetree infrastructure 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
554abe47c7 target/sparc: Partition cpu features 
In the sparc32 binaries, do not advertise features only available
to sparc64, so they cannot be enabled.  In the sparc64 binaries,
do not advertise features mandatory in v9, so they cannot be disabled.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
5f25b383a8 target/sparc: Remove sparcv7 cpu features 
The oldest supported cpu is the microsparc 1; all other cpus
use CPU_DEFAULT_FEATURES.  Remove the features that must always
be present for sparcv7: FLOAT, SWAP, FLUSH, FSQRT, FMUL.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
de1f52032f target/sparc: Use CPU_FEATURE_BIT_* for cpu properties 
Use symbols not integer constants for the bit positions.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
bd7ff659a7 target/sparc: Define features via cpu-feature.h.inc 
Manage feature bits automatically.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
e0f46055a1 target/sparc: Set TCG_GUEST_DEFAULT_MO 
Always use TSO, per the Oracle 2015 manual.
This is slightly less restrictive than the TCG_MO_ALL default,
and happens to match the i386 model, which will eliminate a few
extra barriers on that host.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
d9125cf27c target/sparc: Avoid helper_raise_exception in helper_st_asi 
Always use cpu_raise_exception_ra with GETPC for unwind.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00
Richard Henderson
186e78905a target/sparc: Implement check_align inline 
Emit the exception at the end of the translation block,
so that the non-exception case can fall through.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-10-25 01:01:12 -07:00