Isaku Yamahata a5fce077b1 pci bridge: implement secondary bus reset ...

Trigger secondary bus reset when secondary bus reset bit
value changes from 0 to 1.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

2010-11-22 10:00:07 +02:00

9.4 KiB

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