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Fix build #1

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mcepl merged 1 commits from :main into main 2025-10-28 12:27:34 +01:00
Conversation 2 Commits 1 Files Changed 4 +249 -244
4 changed files with 249 additions and 244 deletions
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184
loong64-support.patch
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@@ -39,9 +39,9 @@ Subject: [PATCH] Add support for LoongArch64
Index: luajit2-2.1-20250826/Makefile
===================================================================
--- luajit2-2.1-20250826.orig/Makefile 2025-10-09 23:13:50.446088447 +0200
+++ luajit2-2.1-20250826/Makefile 2025-10-09 23:13:59.702839100 +0200
@@ -102,6 +102,7 @@
--- luajit2-2.1-20250826.orig/Makefile
+++ luajit2-2.1-20250826/Makefile
@@ -102,6 +102,7 @@ FILES_JITLIB= bc.lua bcsave.lua dump.lua
dis_mips64.lua dis_mips64el.lua \
dis_mips64r6.lua dis_mips64r6el.lua \
dis_riscv.lua dis_riscv64.lua \
@@ -51,8 +51,8 @@ Index: luajit2-2.1-20250826/Makefile
ifeq (,$(findstring Windows,$(OS)))
Index: luajit2-2.1-20250826/dynasm/dasm_loongarch64.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/dynasm/dasm_loongarch64.h 2025-10-09 23:13:59.703032143 +0200
--- /dev/null
+++ luajit2-2.1-20250826/dynasm/dasm_loongarch64.h
@@ -0,0 +1,443 @@
+/*
+** DynASM LoongArch encoding engine.
@@ -499,8 +499,8 @@ Index: luajit2-2.1-20250826/dynasm/dasm_loongarch64.h
+
Index: luajit2-2.1-20250826/dynasm/dasm_loongarch64.lua
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/dynasm/dasm_loongarch64.lua 2025-10-09 23:13:59.703286812 +0200
--- /dev/null
+++ luajit2-2.1-20250826/dynasm/dasm_loongarch64.lua
@@ -0,0 +1,979 @@
+------------------------------------------------------------------------------
+-- DynASM LoongArch module.
@@ -1483,9 +1483,9 @@ Index: luajit2-2.1-20250826/dynasm/dasm_loongarch64.lua
+
Index: luajit2-2.1-20250826/src/Makefile
===================================================================
--- luajit2-2.1-20250826.orig/src/Makefile 2025-10-09 23:13:50.446195839 +0200
+++ luajit2-2.1-20250826/src/Makefile 2025-10-09 23:13:59.703845814 +0200
@@ -53,6 +53,7 @@
--- luajit2-2.1-20250826.orig/src/Makefile
+++ luajit2-2.1-20250826/src/Makefile
@@ -53,6 +53,7 @@ CCOPT_arm64=
CCOPT_ppc=
CCOPT_mips=
CCOPT_riscv64=
@@ -1493,7 +1493,7 @@ Index: luajit2-2.1-20250826/src/Makefile
#
#CCDEBUG=
# Uncomment the next line to generate debug information:
@@ -247,6 +248,10 @@
@@ -247,6 +248,10 @@ else
ifneq (,$(findstring LJ_TARGET_S390X ,$(TARGET_TESTARCH)))
TARGET_LJARCH= s390x
else
@@ -1504,7 +1504,7 @@ Index: luajit2-2.1-20250826/src/Makefile
ifneq (,$(findstring LJ_TARGET_ARM64 ,$(TARGET_TESTARCH)))
ifneq (,$(findstring __AARCH64EB__ ,$(TARGET_TESTARCH)))
TARGET_ARCH= -D__AARCH64EB__=1
@@ -283,6 +288,7 @@
@@ -283,6 +288,7 @@ endif
endif
endif
endif
@@ -1512,7 +1512,7 @@ Index: luajit2-2.1-20250826/src/Makefile
ifneq (,$(findstring LJ_TARGET_PS3 1,$(TARGET_TESTARCH)))
TARGET_SYS= PS3
@@ -352,7 +358,9 @@
@@ -352,7 +358,9 @@ else
# Find out whether the target toolchain always generates unwind tables.
TARGET_TESTUNWIND=$(shell exec 2>/dev/null; echo 'extern void b(void);int a(void){b();return 0;}' | $(TARGET_CC) -c -x c - -o tmpunwind.o && { grep -qa -e eh_frame -e __unwind_info tmpunwind.o || grep -qU -e eh_frame -e __unwind_info tmpunwind.o; } && echo E; rm -f tmpunwind.o)
ifneq (,$(findstring E,$(TARGET_TESTUNWIND)))
@@ -1525,9 +1525,9 @@ Index: luajit2-2.1-20250826/src/Makefile
ifneq (SunOS,$(TARGET_SYS))
Index: luajit2-2.1-20250826/src/host/buildvm.c
===================================================================
--- luajit2-2.1-20250826.orig/src/host/buildvm.c 2025-10-09 23:13:50.441017227 +0200
+++ luajit2-2.1-20250826/src/host/buildvm.c 2025-10-09 23:13:59.704043405 +0200
@@ -71,6 +71,8 @@
--- luajit2-2.1-20250826.orig/src/host/buildvm.c
+++ luajit2-2.1-20250826/src/host/buildvm.c
@@ -71,6 +71,8 @@ static int collect_reloc(BuildCtx *ctx,
#include "../dynasm/dasm_s390x.h"
#elif LJ_TARGET_RISCV64
#include "../dynasm/dasm_riscv.h"
@@ -1538,9 +1538,9 @@ Index: luajit2-2.1-20250826/src/host/buildvm.c
#endif
Index: luajit2-2.1-20250826/src/host/buildvm_asm.c
===================================================================
--- luajit2-2.1-20250826.orig/src/host/buildvm_asm.c 2025-10-09 23:13:50.441145889 +0200
+++ luajit2-2.1-20250826/src/host/buildvm_asm.c 2025-10-09 23:13:59.704166306 +0200
@@ -236,6 +236,15 @@
--- luajit2-2.1-20250826.orig/src/host/buildvm_asm.c
+++ luajit2-2.1-20250826/src/host/buildvm_asm.c
@@ -236,6 +236,15 @@ rv_reloc_err:
ins, sym);
exit(1);
}
@@ -1558,20 +1558,20 @@ Index: luajit2-2.1-20250826/src/host/buildvm_asm.c
#endif
Index: luajit2-2.1-20250826/src/jit/bcsave.lua
===================================================================
--- luajit2-2.1-20250826.orig/src/jit/bcsave.lua 2025-10-09 23:13:50.441296523 +0200
+++ luajit2-2.1-20250826/src/jit/bcsave.lua 2025-10-09 23:13:59.704320697 +0200
@@ -104,6 +104,7 @@
--- luajit2-2.1-20250826.orig/src/jit/bcsave.lua
+++ luajit2-2.1-20250826/src/jit/bcsave.lua
@@ -104,6 +104,7 @@ local map_arch = {
mips64r6el = { e = "le", b = 64, m = 8, f = 0xa0000407, },
s390x = { e = "be", b = 64, m = 22, },
riscv64 = { e = "le", b = 64, m = 243, f = 0x00000004, },
riscv64 = { e = "le", b = 64, m = 243, f = 0x00000004, },
+ loongarch64 = { e = "le", b = 64, m = 258, f = 0x3},
}
local map_os = {
Index: luajit2-2.1-20250826/src/jit/dis_loongarch64.lua
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/jit/dis_loongarch64.lua 2025-10-09 23:13:59.704533056 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/jit/dis_loongarch64.lua
@@ -0,0 +1,697 @@
+----------------------------------------------------------------------------
+-- LuaJIT LoongArch64 disassembler module.
@@ -2272,9 +2272,9 @@ Index: luajit2-2.1-20250826/src/jit/dis_loongarch64.lua
+
Index: luajit2-2.1-20250826/src/lib_jit.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lib_jit.c 2025-10-09 23:13:50.446361090 +0200
+++ luajit2-2.1-20250826/src/lib_jit.c 2025-10-09 23:13:59.704808515 +0200
@@ -867,7 +867,8 @@
--- luajit2-2.1-20250826.orig/src/lib_jit.c
+++ luajit2-2.1-20250826/src/lib_jit.c
@@ -867,7 +867,8 @@ static uint32_t jit_cpudetect(void)
#endif
#elif LJ_TARGET_S390X
/* No optional CPU features to detect (for now). */
@@ -2286,12 +2286,12 @@ Index: luajit2-2.1-20250826/src/lib_jit.c
Index: luajit2-2.1-20250826/src/lj_arch.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_arch.h 2025-10-09 23:13:50.433083022 +0200
+++ luajit2-2.1-20250826/src/lj_arch.h 2025-10-09 23:13:59.704965239 +0200
--- luajit2-2.1-20250826.orig/src/lj_arch.h
+++ luajit2-2.1-20250826/src/lj_arch.h
@@ -35,6 +35,8 @@
#define LUAJIT_ARCH_s390x 8
#define LUAJIT_ARCH_RISCV64 9
#define LUAJIT_ARCH_riscv64 9
#define LUAJIT_ARCH_RISCV64 9
+#define LUAJIT_ARCH_LOONGARCH64 10
+#define LUAJIT_ARCH_loongarch64 10
@@ -2306,7 +2306,7 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
#else
#error "Architecture not supported (in this version), see: https://luajit.org/status.html#architectures"
#endif
@@ -489,6 +493,20 @@
@@ -490,6 +494,20 @@
#define LJ_TARGET_MASKROT 1
#define LJ_ARCH_NUMMODE LJ_NUMMODE_DUAL
@@ -2327,7 +2327,7 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
#else
#error "No target architecture defined"
#endif
@@ -519,6 +537,16 @@
@@ -520,6 +538,16 @@
#error "Need at least GCC 4.8 or newer"
#endif
#endif
@@ -2344,7 +2344,7 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
#elif !LJ_TARGET_PS3
#if __clang__
#if ((__clang_major__ < 3) || ((__clang_major__ == 3) && __clang_minor__ < 5))
@@ -576,6 +604,10 @@
@@ -577,6 +605,10 @@
#if !defined(__riscv_float_abi_double)
#error "Only RISC-V 64 double float supported for now"
#endif
@@ -2357,9 +2357,9 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
Index: luajit2-2.1-20250826/src/lj_asm.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_asm.c 2025-10-09 23:13:50.439989544 +0200
+++ luajit2-2.1-20250826/src/lj_asm.c 2025-10-09 23:13:59.705242972 +0200
@@ -229,6 +229,8 @@
--- luajit2-2.1-20250826.orig/src/lj_asm.c
+++ luajit2-2.1-20250826/src/lj_asm.c
@@ -229,6 +229,8 @@ static Reg rset_pickrandom(ASMState *as,
#include "lj_emit_mips.h"
#elif LJ_TARGET_RISCV64
#include "lj_emit_riscv.h"
@@ -2368,7 +2368,7 @@ Index: luajit2-2.1-20250826/src/lj_asm.c
#else
#error "Missing instruction emitter for target CPU"
#endif
@@ -1714,6 +1716,8 @@
@@ -1714,6 +1716,8 @@ static void asm_loop(ASMState *as)
#include "lj_asm_s390x.h"
#elif LJ_TARGET_RISCV64
#include "lj_asm_riscv64.h"
@@ -2379,8 +2379,8 @@ Index: luajit2-2.1-20250826/src/lj_asm.c
#endif
Index: luajit2-2.1-20250826/src/lj_asm_loongarch64.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/lj_asm_loongarch64.h 2025-10-09 23:14:02.153643630 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/lj_asm_loongarch64.h
@@ -0,0 +1,1990 @@
+/*
+** LoongArch IR assembler (SSA IR -> machine code).
@@ -4374,8 +4374,8 @@ Index: luajit2-2.1-20250826/src/lj_asm_loongarch64.h
+}
Index: luajit2-2.1-20250826/src/lj_ccall.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_ccall.c 2025-10-09 23:13:50.437724513 +0200
+++ luajit2-2.1-20250826/src/lj_ccall.c 2025-10-09 23:14:02.155464354 +0200
--- luajit2-2.1-20250826.orig/src/lj_ccall.c
+++ luajit2-2.1-20250826/src/lj_ccall.c
@@ -778,6 +778,95 @@
} \
}
@@ -4472,7 +4472,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
#else
#error "Missing calling convention definitions for this architecture"
#endif
@@ -1191,6 +1280,53 @@
@@ -1191,6 +1280,53 @@ noth: /* Not a homogeneous float/double
#endif
@@ -4526,7 +4526,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
/* -- Common C call handling ---------------------------------------------- */
/* Infer the destination CTypeID for a vararg argument.
@@ -1245,7 +1381,9 @@
@@ -1245,7 +1381,9 @@ static int ccall_set_args(lua_State *L,
#if LJ_TARGET_RISCV64
int nff = 0;
#endif
@@ -4537,7 +4537,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
/* Clear unused regs to get some determinism in case of misdeclaration. */
memset(cc->gpr, 0, sizeof(cc->gpr));
#if CCALL_NUM_FPR
@@ -1439,7 +1577,7 @@
@@ -1439,7 +1577,7 @@ static int ccall_set_args(lua_State *L,
if (isfp && d->size == sizeof(float))
((uint32_t *)dp)[1] = 0xffffffffu; /* Float NaN boxing */
#endif
@@ -4546,7 +4546,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
if ((ctype_isinteger_or_bool(d->info) || ctype_isenum(d->info)
#if LJ_TARGET_MIPS64
|| (isfp && nsp == 0)
@@ -1487,6 +1625,14 @@
@@ -1487,6 +1625,14 @@ static int ccall_set_args(lua_State *L,
((uint64_t *)dp)[i] = 0xffffffff00000000ul | ((uint32_t *)dp)[i];
} while (i--);
}
@@ -4561,7 +4561,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
#else
UNUSED(isfp);
#endif
@@ -1496,7 +1642,7 @@
@@ -1496,7 +1642,7 @@ static int ccall_set_args(lua_State *L,
if ((int32_t)nsp < 0) nsp = 0;
#endif
@@ -4572,9 +4572,9 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
cc->nsp = (nsp + CTSIZE_PTR-1) & ~(CTSIZE_PTR-1);
Index: luajit2-2.1-20250826/src/lj_ccall.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_ccall.h 2025-10-09 23:13:50.437992427 +0200
+++ luajit2-2.1-20250826/src/lj_ccall.h 2025-10-09 23:13:59.707230811 +0200
@@ -172,6 +172,21 @@
--- luajit2-2.1-20250826.orig/src/lj_ccall.h
+++ luajit2-2.1-20250826/src/lj_ccall.h
@@ -172,6 +172,21 @@ typedef union FPRArg {
struct { LJ_ENDIAN_LOHI(float f; , float g;) };
} FPRArg;
@@ -4596,7 +4596,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.h
#else
#error "Missing calling convention definitions for this architecture"
#endif
@@ -219,7 +234,7 @@
@@ -219,7 +234,7 @@ typedef LJ_ALIGN(CCALL_ALIGN_CALLSTATE)
uint8_t resx87; /* Result on x87 stack: 1:float, 2:double. */
#elif LJ_TARGET_ARM64
void *retp; /* Aggregate return pointer in x8. */
@@ -4607,9 +4607,9 @@ Index: luajit2-2.1-20250826/src/lj_ccall.h
#if LJ_32
Index: luajit2-2.1-20250826/src/lj_ccallback.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_ccallback.c 2025-10-09 23:13:50.438123303 +0200
+++ luajit2-2.1-20250826/src/lj_ccallback.c 2025-10-09 23:13:59.707376084 +0200
@@ -95,6 +95,10 @@
--- luajit2-2.1-20250826.orig/src/lj_ccallback.c
+++ luajit2-2.1-20250826/src/lj_ccallback.c
@@ -95,6 +95,10 @@ static MSize CALLBACK_OFS2SLOT(MSize ofs
#define CALLBACK_MCODE_HEAD 68
@@ -4620,7 +4620,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
#else
/* Missing support for this architecture. */
@@ -330,6 +334,33 @@
@@ -330,6 +334,33 @@ static void *callback_mcode_init(global_
}
return p;
}
@@ -4654,7 +4654,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
#else
/* Missing support for this architecture. */
#define callback_mcode_init(g, p) (p)
@@ -632,6 +663,31 @@
@@ -632,6 +663,31 @@ void lj_ccallback_mcode_free(CTState *ct
if (ngpr < maxgpr) { sp = &cts->cb.gpr[ngpr++]; goto done; } \
}
@@ -4686,7 +4686,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
#elif LJ_TARGET_RISCV64
#define CALLBACK_HANDLE_REGARG \
@@ -812,7 +868,7 @@
@@ -812,7 +868,7 @@ static void callback_conv_result(CTState
*(int64_t *)dp = (int64_t)*(int32_t *)dp;
}
#endif
@@ -4697,8 +4697,8 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
(LJ_ABI_SOFTFP || ctype_isinteger_or_bool(ctr->info)))
Index: luajit2-2.1-20250826/src/lj_emit_loongarch64.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/lj_emit_loongarch64.h 2025-10-09 23:13:59.707601939 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/lj_emit_loongarch64.h
@@ -0,0 +1,306 @@
+/*
+** LoongArch instruction emitter.
@@ -5008,12 +5008,12 @@ Index: luajit2-2.1-20250826/src/lj_emit_loongarch64.h
+#define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
Index: luajit2-2.1-20250826/src/lj_frame.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_frame.h 2025-10-09 23:13:50.434938112 +0200
+++ luajit2-2.1-20250826/src/lj_frame.h 2025-10-09 23:13:59.707792568 +0200
@@ -155,6 +155,15 @@
#define CFRAME_SIZE (10*8)
#define CFRAME_SIZE_JIT (CFRAME_SIZE + 9*16 + 4*8)
#define CFRAME_SHIFT_MULTRES 0
--- luajit2-2.1-20250826.orig/src/lj_frame.h
+++ luajit2-2.1-20250826/src/lj_frame.h
@@ -296,6 +296,15 @@ enum { LJ_CONT_TAILCALL, LJ_CONT_FFI_CAL
#define CFRAME_OFS_MULTRES 0
#define CFRAME_SIZE 256
#define CFRAME_SHIFT_MULTRES 3
+#elif LJ_TARGET_LOONGARCH64
+#define CFRAME_OFS_ERRF 196
+#define CFRAME_OFS_NRES 192
@@ -5024,13 +5024,13 @@ Index: luajit2-2.1-20250826/src/lj_frame.h
+#define CFRAME_OFS_MULTRES 0
+#define CFRAME_SHIFT_MULTRES 3
#else
#define CFRAME_OFS_PREV (4*8)
#if LJ_GC64
#error "Missing CFRAME_* definitions for this architecture"
#endif
Index: luajit2-2.1-20250826/src/lj_gdbjit.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_gdbjit.c 2025-10-09 23:13:50.445038431 +0200
+++ luajit2-2.1-20250826/src/lj_gdbjit.c 2025-10-09 23:13:59.707915800 +0200
@@ -309,6 +309,9 @@
--- luajit2-2.1-20250826.orig/src/lj_gdbjit.c
+++ luajit2-2.1-20250826/src/lj_gdbjit.c
@@ -309,6 +309,9 @@ enum {
#elif LJ_TARGET_RISCV64
DW_REG_SP = 2,
DW_REG_RA = 1,
@@ -5040,7 +5040,7 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
#else
#error "Unsupported target architecture"
#endif
@@ -388,6 +391,8 @@
@@ -388,6 +391,8 @@ static const ELFheader elfhdr_template =
.machine = 8,
#elif LJ_TARGET_RISCV64
.machine = 243,
@@ -5049,7 +5049,7 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
#else
#error "Unsupported target architecture"
#endif
@@ -606,6 +611,13 @@
@@ -606,6 +611,13 @@ static void LJ_FASTCALL gdbjit_ehframe(G
DB(DW_CFA_offset|32|9); DUV(29);
DB(DW_CFA_offset|32|8); DUV(30);
}
@@ -5065,9 +5065,9 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
#endif
Index: luajit2-2.1-20250826/src/lj_jit.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_jit.h 2025-10-09 23:13:50.446533754 +0200
+++ luajit2-2.1-20250826/src/lj_jit.h 2025-10-09 23:13:59.708078957 +0200
@@ -108,6 +108,10 @@
--- luajit2-2.1-20250826.orig/src/lj_jit.h
+++ luajit2-2.1-20250826/src/lj_jit.h
@@ -108,6 +108,10 @@ struct riscv_hwprobe {
#endif
@@ -5078,7 +5078,7 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
#else
#define JIT_F_CPUSTRING ""
@@ -409,7 +413,7 @@
@@ -409,7 +413,7 @@ enum {
LJ_K64_M2P64_31 = LJ_K64_M2P64,
#endif
#endif
@@ -5087,7 +5087,7 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
LJ_K64_2P31, /* 2^31 */
#if LJ_64
LJ_K64_2P63, /* 2^63 */
@@ -418,7 +422,7 @@
@@ -418,7 +422,7 @@ enum {
#endif
LJ_K64__MAX,
};
@@ -5096,7 +5096,7 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
enum {
#if LJ_TARGET_X86ORX64
@@ -428,16 +432,17 @@
@@ -428,16 +432,17 @@ enum {
LJ_K32_2P52_2P31, /* 2^52 + 2^31 */
LJ_K32_2P52, /* 2^52 */
#endif
@@ -5119,9 +5119,9 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
#define LJ_KSIMD(J, n) \
Index: luajit2-2.1-20250826/src/lj_target.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_target.h 2025-10-09 23:13:50.437284165 +0200
+++ luajit2-2.1-20250826/src/lj_target.h 2025-10-09 23:13:59.708231764 +0200
@@ -55,7 +55,7 @@
--- luajit2-2.1-20250826.orig/src/lj_target.h
+++ luajit2-2.1-20250826/src/lj_target.h
@@ -55,7 +55,7 @@ typedef uint32_t RegSP;
/* Bitset for registers. 32 registers suffice for most architectures.
** Note that one set holds bits for both GPRs and FPRs.
*/
@@ -5130,7 +5130,7 @@ Index: luajit2-2.1-20250826/src/lj_target.h
typedef uint64_t RegSet;
#define RSET_BITS 6
#define rset_picktop_(rs) ((Reg)lj_fls64(rs))
@@ -147,6 +147,8 @@
@@ -147,6 +147,8 @@ typedef uint32_t RegCost;
#include "lj_target_s390x.h"
#elif LJ_TARGET_RISCV64
#include "lj_target_riscv.h"
@@ -5141,8 +5141,8 @@ Index: luajit2-2.1-20250826/src/lj_target.h
#endif
Index: luajit2-2.1-20250826/src/lj_target_loongarch64.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/lj_target_loongarch64.h 2025-10-09 23:14:02.156250874 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/lj_target_loongarch64.h
@@ -0,0 +1,313 @@
+/*
+** Definitions for LoongArch CPUs.
@@ -5459,9 +5459,9 @@ Index: luajit2-2.1-20250826/src/lj_target_loongarch64.h
+
Index: luajit2-2.1-20250826/src/lj_trace.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_trace.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_trace.c 2025-10-09 23:13:59.708587403 +0200
@@ -327,17 +327,17 @@
--- luajit2-2.1-20250826.orig/src/lj_trace.c
+++ luajit2-2.1-20250826/src/lj_trace.c
@@ -327,17 +327,17 @@ void lj_trace_initstate(global_State *g)
J->k64[LJ_K64_2P64].u64 = U64x(43f00000,00000000);
J->k32[LJ_K32_M2P64_31] = LJ_64 ? 0xdf800000 : 0xcf000000;
#endif
@@ -5484,9 +5484,9 @@ Index: luajit2-2.1-20250826/src/lj_trace.c
J->k64[LJ_K64_2P63].u64 = U64x(43e00000,00000000);
Index: luajit2-2.1-20250826/src/lj_vmmath.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_vmmath.c 2025-10-09 23:13:50.435766430 +0200
+++ luajit2-2.1-20250826/src/lj_vmmath.c 2025-10-09 23:13:59.708756571 +0200
@@ -70,7 +70,7 @@
--- luajit2-2.1-20250826.orig/src/lj_vmmath.c
+++ luajit2-2.1-20250826/src/lj_vmmath.c
@@ -70,7 +70,7 @@ double lj_vm_foldarith(double x, double
/* -- Helper functions for generated machine code ------------------------- */
#if (LJ_HASJIT && !(LJ_TARGET_ARM || LJ_TARGET_ARM64 || LJ_TARGET_PPC)) || LJ_TARGET_MIPS \
@@ -5497,8 +5497,8 @@ Index: luajit2-2.1-20250826/src/lj_vmmath.c
uint32_t y, ua, ub;
Index: luajit2-2.1-20250826/src/vm_loongarch64.dasc
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/vm_loongarch64.dasc 2025-10-09 23:14:02.156573901 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/vm_loongarch64.dasc
@@ -0,0 +1,4625 @@
+|// Low-level VM code for LoongArch CPUs.
+|// Bytecode interpreter, fast functions and helper functions.

6
luajit.changes
View File

@@ -1,3 +1,9 @@
-------------------------------------------------------------------
Mon Oct 27 14:48:45 UTC 2025 - Andreas Schwab <schwab@suse.de>
- riscv64-support.patch: update from LuaJIT/LuaJIT#1267
- loong64-support.patch: rediff
-------------------------------------------------------------------
Sun Oct 26 20:16:37 UTC 2025 - Matej Cepl <mcepl@cepl.eu>

2
luajit.spec
View File

@@ -35,7 +35,7 @@ URL: https://github.com/openresty/%{name}
Source0: https://github.com/openresty/luajit2/archive/refs/tags/v%{major}-%{minor}.tar.gz#/luajit2-%{major}-%{minor}.tar.gz
Source1: baselibs.conf
# https://patch-diff.githubusercontent.com/raw/openresty/luajit2/pull/236.patch#/riscv64-support.patch#/riscv64-support.patch
# https://patch-diff.githubusercontent.com/raw/openresty/luajit2/pull/236.patch#/riscv64-support.patch
Patch0: riscv64-support.patch
# https://github.com/openresty/luajit2/pull/245/commits/8e40aca7b3a919456b15698273e9b00e9250e769.patch#/loong64-support.patch
Patch1: loong64-support.patch

301
riscv64-support.patch
View File

@@ -1,45 +1,45 @@
From f97b378df83699f05cb34b463f3add4ce70e06a0 Mon Sep 17 00:00:00 2001
From 2578bb041ee4a50f636b00287860f1dd7e7ce860 Mon Sep 17 00:00:00 2001
From: gns <infiwang@proton.me>
Date: Tue, 5 Mar 2024 17:09:31 +0800
Subject: [PATCH 01/22] riscv(support): add RISC-V 64 arch base definition
---
Makefile | 1
dynasm/dasm_riscv.h | 435 ++++
dynasm/dasm_riscv.lua | 979 +++++++++
dynasm/dasm_riscv32.lua | 12
dynasm/dasm_riscv64.lua | 12
src/Makefile | 8
src/host/buildvm.c | 2
src/host/buildvm_asm.c | 31
src/jit/bcsave.lua | 1
src/jit/dis_riscv.lua | 979 +++++++++
src/jit/dis_riscv64.lua | 16
src/lib_jit.c | 121 +
src/lj_alloc.c | 2
src/lj_arch.h | 22
src/lj_asm.c | 4
Makefile | 1 +
dynasm/dasm_riscv.h | 433 +++++
dynasm/dasm_riscv.lua | 979 ++++++++++
dynasm/dasm_riscv32.lua | 12 +
dynasm/dasm_riscv64.lua | 12 +
src/Makefile | 8 +
src/host/buildvm.c | 2 +
src/host/buildvm_asm.c | 31 +
src/jit/bcsave.lua | 1 +
src/jit/dis_riscv.lua | 979 ++++++++++
src/jit/dis_riscv64.lua | 16 +
src/lib_jit.c | 121 ++
src/lj_alloc.c | 2 +-
src/lj_arch.h | 23 +
src/lj_asm.c | 4 +
src/lj_asm_riscv64.h | 2037 ++++++++++++++++++++
src/lj_ccall.c | 156 +
src/lj_ccall.h | 17
src/lj_ccallback.c | 64
src/lj_emit_riscv.h | 574 +++++
src/lj_frame.h | 9
src/lj_gdbjit.c | 15
src/lj_jit.h | 40
src/lj_mcode.c | 17
src/lj_target.h | 4
src/lj_target_riscv.h | 542 +++++
src/lj_vm.h | 3
src/lj_vmmath.c | 3
src/vm_riscv64.dasc | 4813 ++++++++++++++++++++++++++++++++++++++++++++++++
29 files changed, 10912 insertions(+), 7 deletions(-)
src/lj_ccall.c | 156 +-
src/lj_ccall.h | 17 +-
src/lj_ccallback.c | 64 +-
src/lj_emit_riscv.h | 574 ++++++
src/lj_frame.h | 9 +
src/lj_gdbjit.c | 15 +
src/lj_jit.h | 40 +
src/lj_mcode.c | 17 +
src/lj_target.h | 4 +-
src/lj_target_riscv.h | 542 ++++++
src/lj_vm.h | 3 +
src/lj_vmmath.c | 3 +-
src/vm_riscv64.dasc | 4813 +++++++++++++++++++++++++++++++++++++++++++++++
29 files changed, 10911 insertions(+), 7 deletions(-)
Index: luajit2-2.1-20250826/Makefile
===================================================================
--- luajit2-2.1-20250826.orig/Makefile 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/Makefile 2025-10-09 23:13:50.446088447 +0200
@@ -101,6 +101,7 @@
--- luajit2-2.1-20250826.orig/Makefile
+++ luajit2-2.1-20250826/Makefile
@@ -101,6 +101,7 @@ FILES_JITLIB= bc.lua bcsave.lua dump.lua
dis_arm64be.lua dis_ppc.lua dis_mips.lua dis_mipsel.lua \
dis_mips64.lua dis_mips64el.lua \
dis_mips64r6.lua dis_mips64r6el.lua \
@@ -49,15 +49,13 @@ Index: luajit2-2.1-20250826/Makefile
ifeq (,$(findstring Windows,$(OS)))
Index: luajit2-2.1-20250826/dynasm/dasm_riscv.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/dynasm/dasm_riscv.h 2025-10-09 23:13:50.433358410 +0200
@@ -0,0 +1,435 @@
--- /dev/null
+++ luajit2-2.1-20250826/dynasm/dasm_riscv.h
@@ -0,0 +1,433 @@
+/*
+** DynASM RISC-V encoding engine.
+** Copyright (C) 2005-2025 Mike Pall. All rights reserved.
+** Released under the MIT license. See dynasm.lua for full copyright notice.
+**
+** Contributed by gns from PLCT Lab, ISCAS.
+*/
+
+#include <stddef.h>
@@ -489,8 +487,8 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv.h
+
Index: luajit2-2.1-20250826/dynasm/dasm_riscv.lua
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/dynasm/dasm_riscv.lua 2025-10-09 23:13:53.940825099 +0200
--- /dev/null
+++ luajit2-2.1-20250826/dynasm/dasm_riscv.lua
@@ -0,0 +1,979 @@
+------------------------------------------------------------------------------
+-- DynASM RISC-V module.
@@ -920,7 +918,7 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv.lua
+ -- RV32D
+ ["fld_2"] = "00003007FL",
+ ["fsd_2"] = "00003027gS",
+
+
+ ["fmadd.d_4"] = "02000043FGgH",
+ ["fmsub.d_4"] = "02000047FGgH",
+ ["fnmsub.d_4"] = "0200004bFGgH",
@@ -1473,8 +1471,8 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv.lua
+
Index: luajit2-2.1-20250826/dynasm/dasm_riscv32.lua
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/dynasm/dasm_riscv32.lua 2025-10-09 23:13:50.434338754 +0200
--- /dev/null
+++ luajit2-2.1-20250826/dynasm/dasm_riscv32.lua
@@ -0,0 +1,12 @@
+------------------------------------------------------------------------------
+-- DynASM RISC-V 32 module.
@@ -1490,8 +1488,8 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv32.lua
+return require("dasm_riscv")
Index: luajit2-2.1-20250826/dynasm/dasm_riscv64.lua
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/dynasm/dasm_riscv64.lua 2025-10-09 23:13:50.434521368 +0200
--- /dev/null
+++ luajit2-2.1-20250826/dynasm/dasm_riscv64.lua
@@ -0,0 +1,12 @@
+------------------------------------------------------------------------------
+-- DynASM RISC-V 64 module.
@@ -1507,9 +1505,9 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv64.lua
+return require("dasm_riscv")
Index: luajit2-2.1-20250826/src/Makefile
===================================================================
--- luajit2-2.1-20250826.orig/src/Makefile 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/Makefile 2025-10-09 23:13:50.446195839 +0200
@@ -52,6 +52,7 @@
--- luajit2-2.1-20250826.orig/src/Makefile
+++ luajit2-2.1-20250826/src/Makefile
@@ -52,6 +52,7 @@ CCOPT_arm=
CCOPT_arm64=
CCOPT_ppc=
CCOPT_mips=
@@ -1517,7 +1515,7 @@ Index: luajit2-2.1-20250826/src/Makefile
#
#CCDEBUG=
# Uncomment the next line to generate debug information:
@@ -270,6 +271,9 @@
@@ -270,6 +271,9 @@ ifneq (,$(findstring LJ_TARGET_MIPS ,$(T
TARGET_LJARCH= mips
endif
else
@@ -1527,7 +1525,7 @@ Index: luajit2-2.1-20250826/src/Makefile
$(error Unsupported target architecture)
endif
endif
@@ -278,6 +282,7 @@
@@ -278,6 +282,7 @@ endif
endif
endif
endif
@@ -1535,7 +1533,7 @@ Index: luajit2-2.1-20250826/src/Makefile
ifneq (,$(findstring LJ_TARGET_PS3 1,$(TARGET_TESTARCH)))
TARGET_SYS= PS3
@@ -487,6 +492,9 @@
@@ -487,6 +492,9 @@ ifeq (ppc,$(TARGET_LJARCH))
DASM_AFLAGS+= -D ELFV2
endif
endif
@@ -1547,9 +1545,9 @@ Index: luajit2-2.1-20250826/src/Makefile
Index: luajit2-2.1-20250826/src/host/buildvm.c
===================================================================
--- luajit2-2.1-20250826.orig/src/host/buildvm.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/host/buildvm.c 2025-10-09 23:13:50.441017227 +0200
@@ -69,6 +69,8 @@
--- luajit2-2.1-20250826.orig/src/host/buildvm.c
+++ luajit2-2.1-20250826/src/host/buildvm.c
@@ -69,6 +69,8 @@ static int collect_reloc(BuildCtx *ctx,
#include "../dynasm/dasm_mips.h"
#elif LJ_TARGET_S390X
#include "../dynasm/dasm_s390x.h"
@@ -1560,9 +1558,9 @@ Index: luajit2-2.1-20250826/src/host/buildvm.c
#endif
Index: luajit2-2.1-20250826/src/host/buildvm_asm.c
===================================================================
--- luajit2-2.1-20250826.orig/src/host/buildvm_asm.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/host/buildvm_asm.c 2025-10-09 23:13:50.441145889 +0200
@@ -208,6 +208,34 @@
--- luajit2-2.1-20250826.orig/src/host/buildvm_asm.c
+++ luajit2-2.1-20250826/src/host/buildvm_asm.c
@@ -208,6 +208,34 @@ static void emit_asm_wordreloc(BuildCtx
"Error: unsupported opcode %08x for %s symbol relocation.\n",
ins, sym);
exit(1);
@@ -1597,32 +1595,32 @@ Index: luajit2-2.1-20250826/src/host/buildvm_asm.c
#else
#error "missing relocation support for this architecture"
#endif
@@ -304,6 +332,9 @@
@@ -304,6 +332,9 @@ void emit_asm(BuildCtx *ctx)
#if LJ_TARGET_MIPS
fprintf(ctx->fp, "\t.set nomips16\n\t.abicalls\n\t.set noreorder\n\t.set nomacro\n");
#endif
+#if LJ_TARGET_RISCV64
+ fprintf(ctx->fp, ".option arch, -c\n.option norelax\n");
+ fprintf(ctx->fp, ".option norvc\n.option norelax\n");
+#endif
emit_asm_align(ctx, 4);
#if LJ_TARGET_PS3
Index: luajit2-2.1-20250826/src/jit/bcsave.lua
===================================================================
--- luajit2-2.1-20250826.orig/src/jit/bcsave.lua 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/jit/bcsave.lua 2025-10-09 23:13:50.441296523 +0200
@@ -103,6 +103,7 @@
--- luajit2-2.1-20250826.orig/src/jit/bcsave.lua
+++ luajit2-2.1-20250826/src/jit/bcsave.lua
@@ -103,6 +103,7 @@ local map_arch = {
mips64r6 = { e = "be", b = 64, m = 8, f = 0xa0000407, },
mips64r6el = { e = "le", b = 64, m = 8, f = 0xa0000407, },
s390x = { e = "be", b = 64, m = 22, },
+ riscv64 = { e = "le", b = 64, m = 243, f = 0x00000004, },
+ riscv64 = { e = "le", b = 64, m = 243, f = 0x00000004, },
}
local map_os = {
Index: luajit2-2.1-20250826/src/jit/dis_riscv.lua
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/jit/dis_riscv.lua 2025-10-09 23:13:50.445749188 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/jit/dis_riscv.lua
@@ -0,0 +1,979 @@
+------------------------------------------------------------------------------
+-- LuaJIT RISC-V disassembler module.
@@ -2605,8 +2603,8 @@ Index: luajit2-2.1-20250826/src/jit/dis_riscv.lua
+}
Index: luajit2-2.1-20250826/src/jit/dis_riscv64.lua
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/jit/dis_riscv64.lua 2025-10-09 23:13:50.445924448 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/jit/dis_riscv64.lua
@@ -0,0 +1,16 @@
+----------------------------------------------------------------------------
+-- LuaJIT RISC-V 64 disassembler wrapper module.
@@ -2627,9 +2625,9 @@ Index: luajit2-2.1-20250826/src/jit/dis_riscv64.lua
\ No newline at end of file
Index: luajit2-2.1-20250826/src/lib_jit.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lib_jit.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lib_jit.c 2025-10-09 23:13:50.446361090 +0200
@@ -697,6 +697,104 @@
--- luajit2-2.1-20250826.orig/src/lib_jit.c
+++ luajit2-2.1-20250826/src/lib_jit.c
@@ -697,6 +697,104 @@ JIT_PARAMDEF(JIT_PARAMINIT)
#include <sys/utsname.h>
#endif
@@ -2734,7 +2732,7 @@ Index: luajit2-2.1-20250826/src/lib_jit.c
/* Arch-dependent CPU feature detection. */
static uint32_t jit_cpudetect(void)
{
@@ -769,6 +867,29 @@
@@ -769,6 +867,29 @@ static uint32_t jit_cpudetect(void)
#endif
#elif LJ_TARGET_S390X
/* No optional CPU features to detect (for now). */
@@ -2766,9 +2764,9 @@ Index: luajit2-2.1-20250826/src/lib_jit.c
#endif
Index: luajit2-2.1-20250826/src/lj_alloc.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_alloc.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_alloc.c 2025-10-09 23:13:50.445417785 +0200
@@ -365,7 +365,7 @@
--- luajit2-2.1-20250826.orig/src/lj_alloc.c
+++ luajit2-2.1-20250826/src/lj_alloc.c
@@ -365,7 +365,7 @@ static void *CALL_MREMAP_(void *ptr, siz
#define CALL_MREMAP(addr, osz, nsz, mv) CALL_MREMAP_((addr), (osz), (nsz), (mv))
#define CALL_MREMAP_NOMOVE 0
#define CALL_MREMAP_MAYMOVE 1
@@ -2779,14 +2777,14 @@ Index: luajit2-2.1-20250826/src/lj_alloc.c
#define CALL_MREMAP_MV CALL_MREMAP_MAYMOVE
Index: luajit2-2.1-20250826/src/lj_arch.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_arch.h 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_arch.h 2025-10-09 23:13:50.433083022 +0200
--- luajit2-2.1-20250826.orig/src/lj_arch.h
+++ luajit2-2.1-20250826/src/lj_arch.h
@@ -33,6 +33,8 @@
#define LUAJIT_ARCH_mips64 7
#define LUAJIT_ARCH_S390X 8
#define LUAJIT_ARCH_s390x 8
+#define LUAJIT_ARCH_RISCV64 9
+#define LUAJIT_ARCH_riscv64 9
+#define LUAJIT_ARCH_RISCV64 9
/* Target OS. */
#define LUAJIT_OS_OTHER 0
@@ -2799,10 +2797,10 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
#else
#error "Architecture not supported (in this version), see: https://luajit.org/status.html#architectures"
#endif
@@ -470,6 +474,20 @@
#define LJ_ARCH_NUMMODE LJ_NUMMODE_DUAL
@@ -471,6 +475,21 @@
#define LJ_TARGET_GC64 1
#define LJ_ARCH_NOJIT 1 /* NYI */
+#elif LUAJIT_TARGET == LUAJIT_ARCH_RISCV64
+
+#define LJ_ARCH_NAME "riscv64"
@@ -2817,10 +2815,11 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
+#define LJ_TARGET_MASKSHIFT 1
+#define LJ_TARGET_MASKROT 1
+#define LJ_ARCH_NUMMODE LJ_NUMMODE_DUAL
+
#else
#error "No target architecture defined"
@@ -554,6 +572,10 @@
#endif
@@ -554,6 +573,10 @@
#error "Only n64 ABI supported for MIPS64"
#undef LJ_TARGET_MIPS
#endif
@@ -2833,9 +2832,9 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
Index: luajit2-2.1-20250826/src/lj_asm.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_asm.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_asm.c 2025-10-09 23:13:50.439989544 +0200
@@ -227,6 +227,8 @@
--- luajit2-2.1-20250826.orig/src/lj_asm.c
+++ luajit2-2.1-20250826/src/lj_asm.c
@@ -227,6 +227,8 @@ static Reg rset_pickrandom(ASMState *as,
#include "lj_emit_ppc.h"
#elif LJ_TARGET_MIPS
#include "lj_emit_mips.h"
@@ -2844,7 +2843,7 @@ Index: luajit2-2.1-20250826/src/lj_asm.c
#else
#error "Missing instruction emitter for target CPU"
#endif
@@ -1710,6 +1712,8 @@
@@ -1710,6 +1712,8 @@ static void asm_loop(ASMState *as)
#include "lj_asm_mips.h"
#elif LJ_TARGET_S390X
#include "lj_asm_s390x.h"
@@ -2855,8 +2854,8 @@ Index: luajit2-2.1-20250826/src/lj_asm.c
#endif
Index: luajit2-2.1-20250826/src/lj_asm_riscv64.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/lj_asm_riscv64.h 2025-10-09 23:13:53.941477235 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/lj_asm_riscv64.h
@@ -0,0 +1,2037 @@
+/*
+** RISC-V IR assembler (SSA IR -> machine code).
@@ -3554,7 +3553,7 @@ Index: luajit2-2.1-20250826/src/lj_asm_riscv64.h
+ key = ra_alloc1(as, refkey, allow);
+ rset_clear(allow, key);
+ }
+ }
+ }
+
+ /* Key not found in chain: jump to exit (if merged) or load niltv. */
+ l_end = emit_label(as);
@@ -4106,11 +4105,11 @@ Index: luajit2-2.1-20250826/src/lj_asm_riscv64.h
+ emit_ds(as, RISCVI_FCVT_D_L, ftmp, RID_TMP);
+ }
+ emit_ds(as, riscvi, RID_TMP, left);
+ emit_branch(as, RISCVI_BLT, RID_ZERO, RID_TMP, l_end, 0);
+ emit_branch(as, RISCVI_BLT, RID_ZERO, RID_TMP, l_end, -1);
+ emit_dsi(as, RISCVI_ADDI, RID_TMP, RID_TMP, -1075);
+ emit_dsi(as, RISCVI_ANDI, RID_TMP, RID_TMP, 0x7ff);
+ emit_dsi(as, RISCVI_SRLI, RID_TMP, RID_TMP, 52);
+ if (dest != left)
+ if (dest != left)
+ emit_ds1s2(as, RISCVI_FMV_D, dest, left, left);
+ emit_ds(as, RISCVI_FMV_X_D, RID_TMP, left);
+}
@@ -4897,8 +4896,8 @@ Index: luajit2-2.1-20250826/src/lj_asm_riscv64.h
+}
Index: luajit2-2.1-20250826/src/lj_ccall.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_ccall.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_ccall.c 2025-10-09 23:13:50.437724513 +0200
--- luajit2-2.1-20250826.orig/src/lj_ccall.c
+++ luajit2-2.1-20250826/src/lj_ccall.c
@@ -687,6 +687,97 @@
if (ngpr < maxgpr) { dp = &cc->gpr[ngpr++]; goto done; } \
}
@@ -4997,7 +4996,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
#else
#error "Missing calling convention definitions for this architecture"
#endif
@@ -1055,6 +1146,51 @@
@@ -1055,6 +1146,51 @@ static void ccall_copy_struct(CCallState
#endif
@@ -5049,7 +5048,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
/* -- Common C call handling ---------------------------------------------- */
/* Infer the destination CTypeID for a vararg argument.
@@ -1106,6 +1242,10 @@
@@ -1106,6 +1242,10 @@ static int ccall_set_args(lua_State *L,
#endif
#endif
@@ -5060,7 +5059,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
/* Clear unused regs to get some determinism in case of misdeclaration. */
memset(cc->gpr, 0, sizeof(cc->gpr));
#if CCALL_NUM_FPR
@@ -1295,7 +1435,11 @@
@@ -1295,7 +1435,11 @@ static int ccall_set_args(lua_State *L,
*(int64_t *)dp = (int64_t)*(int32_t *)dp;
}
#endif
@@ -5073,7 +5072,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
if ((ctype_isinteger_or_bool(d->info) || ctype_isenum(d->info)
#if LJ_TARGET_MIPS64
|| (isfp && nsp == 0)
@@ -1335,6 +1479,14 @@
@@ -1335,6 +1479,14 @@ static int ccall_set_args(lua_State *L,
CTSize i = (sz >> 2) - 1;
do { ((uint64_t *)dp)[i] = ((uint32_t *)dp)[i]; } while (i--);
}
@@ -5088,7 +5087,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
#else
UNUSED(isfp);
#endif
@@ -1344,7 +1496,7 @@
@@ -1344,7 +1496,7 @@ static int ccall_set_args(lua_State *L,
if ((int32_t)nsp < 0) nsp = 0;
#endif
@@ -5099,9 +5098,9 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
cc->nsp = (nsp + CTSIZE_PTR-1) & ~(CTSIZE_PTR-1);
Index: luajit2-2.1-20250826/src/lj_ccall.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_ccall.h 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_ccall.h 2025-10-09 23:13:50.437992427 +0200
@@ -157,6 +157,21 @@
--- luajit2-2.1-20250826.orig/src/lj_ccall.h
+++ luajit2-2.1-20250826/src/lj_ccall.h
@@ -157,6 +157,21 @@ typedef union FPRArg {
float f;
} FPRArg;
@@ -5123,7 +5122,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.h
#else
#error "Missing calling convention definitions for this architecture"
#endif
@@ -204,7 +219,7 @@
@@ -204,7 +219,7 @@ typedef LJ_ALIGN(CCALL_ALIGN_CALLSTATE)
uint8_t resx87; /* Result on x87 stack: 1:float, 2:double. */
#elif LJ_TARGET_ARM64
void *retp; /* Aggregate return pointer in x8. */
@@ -5134,9 +5133,9 @@ Index: luajit2-2.1-20250826/src/lj_ccall.h
#if LJ_32
Index: luajit2-2.1-20250826/src/lj_ccallback.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_ccallback.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_ccallback.c 2025-10-09 23:13:50.438123303 +0200
@@ -91,6 +91,10 @@
--- luajit2-2.1-20250826.orig/src/lj_ccallback.c
+++ luajit2-2.1-20250826/src/lj_ccallback.c
@@ -91,6 +91,10 @@ static MSize CALLBACK_OFS2SLOT(MSize ofs
#define CALLBACK_MCODE_HEAD 52
@@ -5147,7 +5146,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
#else
/* Missing support for this architecture. */
@@ -293,6 +297,39 @@
@@ -293,6 +297,39 @@ static void *callback_mcode_init(global_
}
return p;
}
@@ -5187,7 +5186,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
#else
/* Missing support for this architecture. */
#define callback_mcode_init(g, p) (p)
@@ -595,6 +632,31 @@
@@ -595,6 +632,31 @@ void lj_ccallback_mcode_free(CTState *ct
if (ngpr < maxgpr) { sp = &cts->cb.gpr[ngpr++]; goto done; } \
}
@@ -5219,7 +5218,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
#else
#error "Missing calling convention definitions for this architecture"
#endif
@@ -750,7 +812,7 @@
@@ -750,7 +812,7 @@ static void callback_conv_result(CTState
*(int64_t *)dp = (int64_t)*(int32_t *)dp;
}
#endif
@@ -5230,8 +5229,8 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
(LJ_ABI_SOFTFP || ctype_isinteger_or_bool(ctr->info)))
Index: luajit2-2.1-20250826/src/lj_emit_riscv.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/lj_emit_riscv.h 2025-10-09 23:13:53.942748326 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/lj_emit_riscv.h
@@ -0,0 +1,574 @@
+/*
+** RISC-V instruction emitter.
@@ -5461,7 +5460,7 @@ Index: luajit2-2.1-20250826/src/lj_emit_riscv.h
+ lj_assertA(0, "invalid ext op");
+ return;
+ }
+ emit_dsshamt(as, sri, rd, rd, shamt);
+ emit_dsshamt(as, sri, rd, rd, shamt);
+ emit_dsshamt(as, sli, rd, rs1, shamt);
+ }
+}
@@ -5809,9 +5808,9 @@ Index: luajit2-2.1-20250826/src/lj_emit_riscv.h
+#define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
Index: luajit2-2.1-20250826/src/lj_frame.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_frame.h 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_frame.h 2025-10-09 23:13:50.434938112 +0200
@@ -287,6 +287,15 @@
--- luajit2-2.1-20250826.orig/src/lj_frame.h
+++ luajit2-2.1-20250826/src/lj_frame.h
@@ -287,6 +287,15 @@ enum { LJ_CONT_TAILCALL, LJ_CONT_FFI_CAL
** need to change to 3.
*/
#define CFRAME_SHIFT_MULTRES 0
@@ -5829,9 +5828,9 @@ Index: luajit2-2.1-20250826/src/lj_frame.h
#endif
Index: luajit2-2.1-20250826/src/lj_gdbjit.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_gdbjit.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_gdbjit.c 2025-10-09 23:13:50.445038431 +0200
@@ -306,6 +306,9 @@
--- luajit2-2.1-20250826.orig/src/lj_gdbjit.c
+++ luajit2-2.1-20250826/src/lj_gdbjit.c
@@ -306,6 +306,9 @@ enum {
#elif LJ_TARGET_MIPS
DW_REG_SP = 29,
DW_REG_RA = 31,
@@ -5841,7 +5840,7 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
#else
#error "Unsupported target architecture"
#endif
@@ -383,6 +386,8 @@
@@ -383,6 +386,8 @@ static const ELFheader elfhdr_template =
.machine = 20,
#elif LJ_TARGET_MIPS
.machine = 8,
@@ -5850,7 +5849,7 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
#else
#error "Unsupported target architecture"
#endif
@@ -591,6 +596,16 @@
@@ -591,6 +596,16 @@ static void LJ_FASTCALL gdbjit_ehframe(G
for (i = 23; i >= 16; i--) { DB(DW_CFA_offset|i); DUV(26-i); }
for (i = 30; i >= 20; i -= 2) { DB(DW_CFA_offset|32|i); DUV(42-i); }
}
@@ -5869,8 +5868,8 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
#endif
Index: luajit2-2.1-20250826/src/lj_jit.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_jit.h 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_jit.h 2025-10-09 23:13:50.446533754 +0200
--- luajit2-2.1-20250826.orig/src/lj_jit.h
+++ luajit2-2.1-20250826/src/lj_jit.h
@@ -68,6 +68,46 @@
#endif
#endif
@@ -5920,8 +5919,8 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
#define JIT_F_CPUSTRING ""
Index: luajit2-2.1-20250826/src/lj_mcode.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_mcode.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_mcode.c 2025-10-09 23:13:50.445281779 +0200
--- luajit2-2.1-20250826.orig/src/lj_mcode.c
+++ luajit2-2.1-20250826/src/lj_mcode.c
@@ -38,6 +38,12 @@
void sys_icache_invalidate(void *start, size_t len);
#endif
@@ -5935,7 +5934,7 @@ Index: luajit2-2.1-20250826/src/lj_mcode.c
/* Synchronize data/instruction cache. */
void lj_mcode_sync(void *start, void *end)
{
@@ -52,6 +58,17 @@
@@ -52,6 +58,17 @@ void lj_mcode_sync(void *start, void *en
sys_icache_invalidate(start, (char *)end-(char *)start);
#elif LJ_TARGET_PPC
lj_vm_cachesync(start, end);
@@ -5955,9 +5954,9 @@ Index: luajit2-2.1-20250826/src/lj_mcode.c
#else
Index: luajit2-2.1-20250826/src/lj_target.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_target.h 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_target.h 2025-10-09 23:13:50.437284165 +0200
@@ -55,7 +55,7 @@
--- luajit2-2.1-20250826.orig/src/lj_target.h
+++ luajit2-2.1-20250826/src/lj_target.h
@@ -55,7 +55,7 @@ typedef uint32_t RegSP;
/* Bitset for registers. 32 registers suffice for most architectures.
** Note that one set holds bits for both GPRs and FPRs.
*/
@@ -5966,7 +5965,7 @@ Index: luajit2-2.1-20250826/src/lj_target.h
typedef uint64_t RegSet;
#define RSET_BITS 6
#define rset_picktop_(rs) ((Reg)lj_fls64(rs))
@@ -145,6 +145,8 @@
@@ -145,6 +145,8 @@ typedef uint32_t RegCost;
#include "lj_target_mips.h"
#elif LJ_TARGET_S390X
#include "lj_target_s390x.h"
@@ -5977,8 +5976,8 @@ Index: luajit2-2.1-20250826/src/lj_target.h
#endif
Index: luajit2-2.1-20250826/src/lj_target_riscv.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/lj_target_riscv.h 2025-10-09 23:13:50.437461959 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/lj_target_riscv.h
@@ -0,0 +1,542 @@
+/*
+** Definitions for RISC-V CPUs.
@@ -6524,9 +6523,9 @@ Index: luajit2-2.1-20250826/src/lj_target_riscv.h
+#endif
Index: luajit2-2.1-20250826/src/lj_vm.h
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_vm.h 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_vm.h 2025-10-09 23:13:50.435674046 +0200
@@ -37,6 +37,9 @@
--- luajit2-2.1-20250826.orig/src/lj_vm.h
+++ luajit2-2.1-20250826/src/lj_vm.h
@@ -37,6 +37,9 @@ LJ_ASMF int lj_vm_cpuid(uint32_t f, uint
#if LJ_TARGET_PPC
void lj_vm_cachesync(void *start, void *end);
#endif
@@ -6538,9 +6537,9 @@ Index: luajit2-2.1-20250826/src/lj_vm.h
LJ_ASMF double lj_vm_foldfpm(double x, int op);
Index: luajit2-2.1-20250826/src/lj_vmmath.c
===================================================================
--- luajit2-2.1-20250826.orig/src/lj_vmmath.c 2025-08-26 14:24:06.000000000 +0200
+++ luajit2-2.1-20250826/src/lj_vmmath.c 2025-10-09 23:13:50.435766430 +0200
@@ -69,7 +69,8 @@
--- luajit2-2.1-20250826.orig/src/lj_vmmath.c
+++ luajit2-2.1-20250826/src/lj_vmmath.c
@@ -69,7 +69,8 @@ double lj_vm_foldarith(double x, double
/* -- Helper functions for generated machine code ------------------------- */
@@ -6552,14 +6551,15 @@ Index: luajit2-2.1-20250826/src/lj_vmmath.c
uint32_t y, ua, ub;
Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ luajit2-2.1-20250826/src/vm_riscv64.dasc 2025-10-09 23:13:53.943164149 +0200
--- /dev/null
+++ luajit2-2.1-20250826/src/vm_riscv64.dasc
@@ -0,0 +1,4813 @@
+|// Low-level VM code for RISC-V 64 CPUs.
+|// Bytecode interpreter, fast functions and helper functions.
+|// Copyright (C) 2005-2025 Mike Pall. See Copyright Notice in luajit.h
+|//
+|// Contributed by gns from PLCT Lab, ISCAS.
+|// Sponsored by PLCT Lab, ISCAS.
+|
+|.arch riscv64
+|.section code_op, code_sub
@@ -7623,7 +7623,7 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ |->vmeta_istype:
+ | addi PC, PC, -4
+ | sd BASE, L->base
+ | mv CARG1, L
+ | mv CARG1, L
+ | srliw CARG2, RA, 3
+ | srliw CARG3, RD, 3
+ | sd PC, SAVE_PC(sp)
@@ -9590,14 +9590,13 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ | // RA = dst*8 or unused, RD = src*8, JMP with RD = target
+ | add RD, BASE, RD
+ | lhu TMP2, OFS_RD(PC)
+ | ld TMP0, 0(RD)
+ | ld CRET1, 0(RD)
+ | addi PC, PC, 4
+ | gettp TMP0, TMP0
+ | gettp TMP0, CRET1
+ | add RA, BASE, RA
+ | sltiu TMP0, TMP0, LJ_TISTRUECOND // TMP0=1 true; TMP0=0 false
+ | decode_BC4b TMP2
+ | lui TMP3, (-(BCBIAS_J*4 >> 12)) & 0xfffff // -BCBIAS_J*4
+ | ld CRET1, 0(RD)
+ | addw TMP2, TMP2, TMP3 // (jump-0x8000)<<2
+ if (op == BC_IST || op == BC_ISTC) {
+ | beqz TMP0, >1
@@ -9667,8 +9666,9 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ | lui TMP1, 0x80000
+ | gettp CARG3, TMP0
+ | bne CARG3, TISNUM, >1
+ | negw TMP0, TMP0
+ | sext.w TMP0, TMP0
+ | bxeq TMP0, TMP1, ->vmeta_unm // Meta handler deals with -2^31.
+ | negw TMP0, TMP0
+ | zext.w TMP0, TMP0
+ | settp_b TMP0, TISNUM
+ | j >2
@@ -9767,7 +9767,7 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ | ins_next2
+ |.endmacro
+ |
+ |.macro ins_arithead, itype1, itype2, tval1, tval2
+ |.macro ins_arithead, itype1, itype2, tval1, tval2
+ | ld tval1, 0(RB)
+ | ld tval2, 0(RC)
+ | // Check for two integers.
@@ -9833,7 +9833,7 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ |1: // Check for two numbers.
+ | ins_arithfp, fpins, TMP0, TMP1
+ |.endmacro
+
+
+ case BC_ADDVN: case BC_ADDNV: case BC_ADDVV:
+ | ins_arithdn addw, fadd.d
+ break;
@@ -10380,9 +10380,9 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ | ld TAB:TMP0, TAB:RB->metatable
+ | beq CARG2, TISNIL, >4 // Key found, but nil value?
+ |2:
+ | andi TMP3, TMP3, LJ_GC_BLACK // isblack(table)
+ | andi TMP4, TMP3, LJ_GC_BLACK // isblack(table)
+ | fsd FTMP0, NODE:TMP2->val
+ | bnez TMP3, >7
+ | bnez TMP4, >7
+ |3:
+ | ins_next
+ |
@@ -10555,11 +10555,10 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ case BC_CALLMT:
+ | // RA = base*8, (RB = 0,) RC = extra_nargs*8
+ | addw NARGS8:RD, NARGS8:RD, MULTRES
+ | j ->BC_CALLT_Z1
+ | // Fall through. Assumes BC_CALLT follows.
+ break;
+ case BC_CALLT:
+ | // RA = base*8, (RB = 0,) RC = (nargs+1)*8
+ |->BC_CALLT_Z1:
+ | add RA, BASE, RA
+ | ld LFUNC:RB, 0(RA)
+ | mv NARGS8:RC, RD
@@ -10805,12 +10804,11 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ case BC_RETM:
+ | // RA = results*8, RD = extra_nresults*8
+ | addw RD, RD, MULTRES
+ | j ->BC_RET_Z1
+ | // Fall through. Assumes BC_RET follows.
+ break;
+
+ case BC_RET:
+ | // RA = results*8, RD = (nresults+1)*8
+ |->BC_RET_Z1:
+ | ld PC, FRAME_PC(BASE)
+ | add RA, BASE, RA
+ | mv MULTRES, RD
@@ -10843,8 +10841,9 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
+ | ld LFUNC:TMP1, FRAME_FUNC(BASE)
+ | cleartp LFUNC:TMP1
+ | ld TMP1, LFUNC:TMP1->pc
+ | ins_next1
+ | ld KBASE, PC2PROTO(k)(TMP1)
+ | ins_next
+ | ins_next2
+ |
+ |6: // Fill up results with nil.
+ | sd TISNIL, 0(TMP2)