* riscv - disassembly now supports -M,max
* nios2 - support dropped except in readelf
* assembler:
- x86: add support for AMX-AVX512, AMX-FP8, AMX-MOVRS, AMX-TF32
and AMX-TRANSPOSE, MOVRS, PHE2, RNG2, GMI, MSR_IMM instructions
- x86: add support for Intel AVX10.2 and SM4 AVX10.2 extensions
- aarch64: SME and SVE non-widening BFloat16 instructions
- riscv: various standard and vendor extensions added:
Zicfiss v1.0, Zicfilp v1.0, Zcmp v1.0, Zcmt v1.0,
Smrnmi v1.0, S[sm]dbltrp v1.0 and S[sm]ctr v1.0;
CORE-V: xcvbitmanip v1.0 and xcvsimd v1.0;
SiFive: xsfvqmaccdod v1.0, xsfvqmaccqoqv1.0 and xsfvfnrclipxfqf v1.0
* linker:
- loongarch: changed default max page size from 16KiB to 64KiB
- add support for mixed LTO and non-LTO code in relocatable output
- add --image-base=<ADDR> to behave like -Ttext-segment for
compatibility with LLD
- Accept percent-encoded and %[string] encoded JSON payload
with --package-metadata
- binutils-gold is gone for good.
OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=489
This gives us loongarch, new s390 insns (for SLE), and for now
avoid the issue with zstd we had in the last submission (by not
using it by default). It's also what is going to be in SLE-15
soon.
- Update to current 2.43.1 branch [PED-10254, PED-10306]:
* s390 - Add arch15 instructions
* various fixes from upstream: PR32153, PR32171, PR32189,
PR32196, PR32191, PR32109, PR32372, PR32387
- Adjusted binutils-2.43-branch.diff.gz.
- Disable zstd-by-default again (needs adjustments in at least
golang,llvm15,llvm17 first)
- Add binutils-fix-branch.diff.
- Check non-changing of flex/bison inputs only after applying
branch and fix-branch diffs.
- drop ld-relro.diff (relro is the default for some time)
and it warns on avr spuriously (bsc#1233520)
- Add loongarch64 as new target
- Enable zstd compression algorithm (instead of zlib)
for debug info sections by default.
OBS-URL: https://build.opensuse.org/request/show/1229830
OBS-URL: https://build.opensuse.org/package/show/openSUSE:Factory/binutils?expand=0&rev=174
- Update to version 2.43:
* new .base64 pseudo-op, allowing base64 encoded data as strings
* Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF
(APX_F now fully supported)
* x86 Intel syntax now warns about more mnemonic suffixes
* macros and .irp/.irpc/.rept bodies can use \+ to get at number
of times the macro/body was executed
* aarch64: support 'armv9.5-a' for -march, add support for LUT
and LUT2
* s390: base register operand in D(X,B) and D(L,B) can now be
omitted (ala 'D(X,)'); warn when register type doesn't match
operand type (use option
'warn-regtype-mismatch=[strict|relaxed|no]' to adjust)
* riscv: support various extensions: Zacas, Zcmp, Zfbfmin,
Zvfbfmin, Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw,
XSfCease, all at version 1.0;
remove support for assembly of privileged spec 1.9.1 (linking
support remains)
* arm: remove support for some old co-processors: Maverick and FPA
* mips: '--trap' now causes either trap or breakpoint instructions
to be emitted as per current ISA, instead of always using trap
insn and failing when current ISA was incompatible with that
* LoongArch: accept .option pseudo-op for fine-grained control
of assembly code options; add support for DT_RELR
* readelf: now displays RELR relocations in full detail;
add -j/--display-section to show just those section(s) content
according to their type
* objdump/readelf now dump also .eh_frame_hdr (when present) when
dumping .eh_frame
* gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake
OBS-URL: https://build.opensuse.org/request/show/1193447
OBS-URL: https://build.opensuse.org/package/show/openSUSE:Factory/binutils?expand=0&rev=172
* new .base64 pseudo-op, allowing base64 encoded data as strings
* Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF
(APX_F now fully supported)
* x86 Intel syntax now warns about more mnemonic suffixes
* macros and .irp/.irpc/.rept bodies can use \+ to get at number of times
the macro/body was executed
* aarch64: support 'armv9.5-a' for -march, add support for LUT and LUT2
* s390: base register operand in D(X,B) and D(L,B) can now be omitted
(ala 'D(X,)'); warn when register type doesn't match operand type
(use option 'warn-regtype-mismatch=[strict|relaxed|no]' to adjust)
* riscv: support various extensions: Zacas, Zcmp, Zfbfmin, Zvfbfmin,
Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw, XSfCease, all at
version 1.0;
remove support for assembly of privileged spec 1.9.1 (linking support
remains)
* arm: remove support for some old co-processors: Maverick and FPA
* mips: '--trap' now causes either trap or breakpoint instructions to
be emitted as per current ISA, instead of always using trap insn
and failing when current ISA was incompatible with that
* LoongArch: accept .option pseudo-op for fine-grained control
of assembly code options; add support for DT_RELR
* readelf: now displays RELR relocations in full detail;
add -j/--display-section to show just those section(s) content
according to their type
* objdump/readelf now dump also .eh_frame_hdr (when present) when
dumping .eh_frame
* gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake processors;
add minimal support for riscv
* linker:
OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=471
