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OBS-URL: https://build.opensuse.org/package/show/utilities/cpuid?expand=0&rev=46
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Jan Engelhardt 2023-04-14 10:37:40 +00:00 committed by Git OBS Bridge
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Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich <eich@suse.com> Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich <eich@suse.com>
- Update to release 20230406: - Update to release 20230406:
* Fixed bug when interpreting leaf 0xb and 0x1f bit widths: * Support APIC bit fields for the newest 4 topology layers:
Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1 module, tile, die, die group.
in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID
values.
* For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of
level & previous levels" to reflect this definition.
* Support APIC bit fields for the newest 4 topology
layers: module, tile, die, die group. And for the mp version, also
the older cu & pkg levels.
* Use the extended APIC ID's when available in a variety of leaves.
* Support leaf 0xb method for AMD/Hygon. * Support leaf 0xb method for AMD/Hygon.
* Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS. * Added prelim Bergamo A1 stepping from sample.
* Added 7/1/edx AMX-COMPLEX instructions. * Added AMX-COMPLEX instructions, UC-lock disable,
* Added 7/2/edx UC-lock disable. non-contiguous 1s value support, event logging supported
* Added 0x10/n/ecx non-contiguous 1s value supported. bitmap.
* Added 0x1c/ecx event logging supported bitmap.
* Added 0x23/0/ebx decoding.
* Decode 0x80000026/1/ebx core type & native model.
* For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match
Intel versions in 7/1/eax.
* For 0x80000022/ecx, shorten description, show bitmask only in
hex.
* Update CPUID utility with new feature bits as documented in * Update CPUID utility with new feature bits as documented in
the AMD Processor Programming Reference for Family 19h and Model 11h: the AMD Processor Programming Reference for Family 19h and
0x8000000a/edx extended LVT offset fault change Model 11h: extended LVT offset fault cange, enhanced
0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC, predictive store forwarding, FSRS, FSRC,
FsGsKernelGsBaseNonSerializing FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
0x80000022/ebx number of available UMC PMCs bitmask representing active UMCs.
0x80000022/ecx bitmask representing active UMCs * Added (synth) decoding for Sapphire Rapids D & E0 steppings
* Differentiate preliminary (uarch synth) for (0,6),(10,10); * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
(0,6),(10,11); (0,6),(10,12); and (0,6),(11,5) Crestmont Atom cores Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
from their Redwood Cove counterparts. Raptor Lake-H/U/P.
* Added preliminary (synth) & (uarch synth) for (0,6),(12,6)
Lion Cove & Skymont, from LX*.
* Added 12/0/eax SGX ENCLS EUPDATESVN bit.
* Added 0x1f/*/ecx level type value "die group (6)".
* Added (synth) decoding for (0,6),(8,15) Sapphire Rapids D &
E0 steppings from coreboot*.
* Improved (synth) decoding for (0,6),(6,10) Scalable 3rd Gen
Xeons to Ice Lake-SP. Also, improved decoding for engr samples where
the brand string omits Xeon & Bronze/Silver/Gold/Platinum.
* Improved (synth) decoding for (0,6),(11,14) Intel N-Series.
* Differentiate (synth) & (uarch synth) for (0,6),(11,14) * Differentiate (synth) & (uarch synth) for (0,6),(11,14)
Alder Lake-N based on core type, much like for other Alder Lake models. Alder Lake-N based on core type.
This corrects the cores to Gracemont. As for Golden Cove, perhaps * Differentiate Lakefield P-cores from Tremont E-cores.
P-cores never will exist for this model but, if they do, they should * Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
now be decoded correctly. * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
* Updated (synth) decoding for (0,6),(11,15),5 with Raptor Lake-S/HX/P. * Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
* Updated (synth) decoding for (0,6),(11,10) with Raptor Lake-H/U/P. Cezanne/Barcelo, Raphael, and Phoenix, based on their
* Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made respective PPPRs.
the following (synth) changes: * Added Alder Lake Core names: i*-12000.
* Updated (0,6),(3,7),8 Bay Trail with stepping name C0.
* Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping.
* Corrected (0,6),(4,6),1 Crystal Well to C0 stepping.
* Updated (0,6),(4,7),1 Broadwell to include E0 stepping.
* Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable).
* Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable).
* Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable).
* Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0
steppings.
* Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable).
* Added (0,6),(6,12),1 Ice Lake B0.
* Updated (0,6),(8,6),4 Snow Ridge with stepping B0.
* Updated (0,6),(8,6),5 Snow Ridge with stepping B1.
* Added (0,6),(8,6),1 Lakefield B2/B3 stepping.
* Corrected (0,6),(8,12),1 Tiger Lake stepping to B1.
* Added (0,6),(8,12),2 Tiger Lake C0.
* Added (0,6),(8,14),10 Coffee Lake D0.
* Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping.
* Added (0,6),(8,15) Sapphire Rapids numerous steppings.
* Updated (0,6),(9,12) Jasper Lake with stepping A1.
* Differentiate (0,6),(8,10) Lakefield P-cores from Tremont
E-cores, much as I previously did for Alder Lake & Raptor Lake.
* For known Hybrid chips (Alder Lake, Raptor Lake & Lakefield),
only decode the uarch if it's one of the two known hybrid types.
However, some (0,6),(9,7) Alder Lake's are non-hybrid (Golden Cove only),
so also decode core type == 0x00 there.
* In the Intel Core era, uarch families are identified only by
the initial uarch in the family. So the family names in {braces},
which also are uarch names, can be confusing. So, change (synth) and
(uarch synth) for those families to explain the relationships between
the subsequent uarch and the initial uarch, in the form of
"shrink of", "optim of", and the unusual "backport of".
* Added (4th Gen) to the (synth) description of (10,15),(1,*)
AMD EPYC Genoa.
* Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2
CPUs to claim 4nm process.
* Corrected 7/1/eax fast REP instructions, where I'd left the
REP prefix out of the description.
* Added 7/1/eax FRED & LKGS bits, from Intel Flexible Return and
Event Deliver (FRED).
* Clarified 7/1/eax ArchPerfmonExt, which indicates that leaf
0x23 is valid.
* Added (uarch synth) decoding for AMD Ryzen (Phoenix E0), based
on sample from bakerlab.org, which I missed on Oct 3 2022, when I
added the (synth) decoding.
* Added 0x80000001/ebx PkgType decoding for AMD (10,15) Family
19h CPUs: (2,1) Vermeer, (5,1) Cezanne/Barcelo, (6,1) Raphael, and
(7,0) Phoenix, based on their respective PPPR's.
* Added very early (synth) decoding for Lunar Lake. There is
no corresponding (uarch synth) decoding, because no name is yet known
for the uarch.
* Added (0,6),(9,10) Alder Lake Core names: i*-12000.
* Differentiate (0,6),(9,7) & (0,6),(9,10) Alder Lake Gracemont
E-cores from Golden Cove P-cores.
* Differentiate (0,6),(11,7); (0,6),(11,10) & (0,6),(11,15)
Raptor Lake Gracemont E-cores from Raptor Cove P-cores.
* Added (synth) & (uarch synth) decoding for (10,15),(7,8)
Phoenix 2, from Coreboot*.
* Decode Xen tsc mode. * Decode Xen tsc mode.
* Added (synth) decoding for (10,15),(6,1,1) Raphael B1.
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Sat Jan 28 19:47:27 UTC 2023 - Dirk Müller <dmueller@suse.com> Sat Jan 28 19:47:27 UTC 2023 - Dirk Müller <dmueller@suse.com>