- Bump to 910735c5d7ce7607384fc1eec4189e90c8ae5c84, git7256.

* Includes GCC 13.1 release and first bugfixes
- Update riscv-atomic.patch from the version committed upstream.

OBS-URL: https://build.opensuse.org/package/show/devel:gcc/gcc13?expand=0&rev=45

cross-aarch64-gcc13-bootstrap.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-aarch64-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-amdgcn-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-arm-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-arm-none-gcc13-bootstrap.spec

@@ -108,7 +108,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-arm-none-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-avr-gcc13-bootstrap.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-avr-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-bpf-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-epiphany-gcc13-bootstrap.spec

@@ -108,7 +108,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-epiphany-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-hppa-gcc13-bootstrap.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-hppa-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-m68k-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-mips-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-nvptx-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-ppc64-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-ppc64le-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-pru-gcc13-bootstrap.spec

@@ -108,7 +108,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-pru-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-riscv64-elf-gcc13-bootstrap.spec

@@ -108,7 +108,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-riscv64-elf-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-riscv64-gcc13-bootstrap.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-riscv64-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-rx-gcc13-bootstrap.spec

@@ -108,7 +108,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-rx-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-s390x-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-sparc-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-sparc64-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

cross-x86_64-gcc13.spec

@@ -107,7 +107,7 @@ Name:           %{pkgname}
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

gcc-13.1.1+git7256.tar.xz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:dbed814f4ff143ad4d4cfc53a3ccdce5b5ff12de30f856dc262290d4f0dc4911
+size 87952832

gcc.spec.in

@@ -204,7 +204,7 @@
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:          https://gcc.gnu.org/
-Version: 13.0.1+git7231
+Version: 13.1.1+git7256
 Release:      1
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

gcc13-testresults.spec

@@ -221,7 +221,7 @@
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

gcc13.changes

@@ -1,3 +1,10 @@
+-------------------------------------------------------------------
+Thu Apr 27 07:29:05 UTC 2023 - Richard Biener <rguenther@suse.com>
+
+- Bump to 910735c5d7ce7607384fc1eec4189e90c8ae5c84, git7256.
+  * Includes GCC 13.1 release and first bugfixes
+- Update riscv-atomic.patch from the version committed upstream.
+
 -------------------------------------------------------------------
 Fri Apr 21 06:46:36 UTC 2023 - Richard Biener <rguenther@suse.com>
 

gcc13.spec

@@ -200,7 +200,7 @@
 %define biarch_targets x86_64 s390x powerpc64 powerpc sparc sparc64
 
 URL:            https://gcc.gnu.org/
-Version:        13.0.1+git7231
+Version:        13.1.1+git7256
 Release:        0
 %define gcc_dir_version %(echo %version |  sed 's/+.*//' | cut -d '.' -f 1)
 %define gcc_snapshot_revision %(echo %version | sed 's/[3-9]\.[0-9]\.[0-6]//' | sed 's/+/-/')

riscv-atomic.patch

@@ -1,7 +1,8 @@
-From e64a2e73f03404f61387cf736ea0e422f8797862 Mon Sep 17 00:00:00 2001
+From 5535cd3443b2906778e4f1850c5dd0b2af5f07e8 Mon Sep 17 00:00:00 2001
 From: Patrick O'Neill <patrick@rivosinc.com>
-Date: Tue, 19 Apr 2022 10:17:50 -0700
-Subject: [PATCH] RISC-V: Add support for inlining subword atomic operations
+Date: Tue, 18 Apr 2023 14:33:13 -0700
+Subject: [PATCH] RISCV: Inline subword atomic ops
+To: gcc-patches@gcc.gnu.org
 
 RISC-V has no support for subword atomic operations; code currently
 generates libatomic library calls.
@@ -15,34 +16,42 @@ gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
 This will need to stay for backwards compatibility and the
 -mno-inline-atomics flag.
 
-2022-04-19 Patrick O'Neill <patrick@rivosinc.com>
+2023-04-18 Patrick O'Neill <patrick@rivosinc.com>
 
+gcc/ChangeLog:
 	PR target/104338
-	* riscv-protos.h: Add helper function stubs.
-	* riscv.cc: Add helper functions for subword masking.
-	* riscv.opt: Add command-line flag.
-	* sync.md: Add masking logic and inline asm for fetch_and_op,
+	* config/riscv/riscv-protos.h: Add helper function stubs.
+	* config/riscv/riscv.cc: Add helper functions for subword masking.
+	* config/riscv/riscv.opt: Add command-line flag.
+	* config/riscv/sync.md: Add masking logic and inline asm for fetch_and_op,
 	fetch_and_nand, CAS, and exchange ops.
-	* invoke.texi: Add blurb regarding command-line flag.
-	* inline-atomics-1.c: New test.
-	* inline-atomics-2.c: Likewise.
-	* inline-atomics-3.c: Likewise.
-	* inline-atomics-4.c: Likewise.
-	* inline-atomics-5.c: Likewise.
-	* inline-atomics-6.c: Likewise.
-	* inline-atomics-7.c: Likewise.
-	* inline-atomics-8.c: Likewise.
-	* atomic.c: Add reference to duplicate logic.
+	* doc/invoke.texi: Add blurb regarding command-line flag.
+
+libgcc/ChangeLog:
+	PR target/104338
+	* config/riscv/atomic.c: Add reference to duplicate logic.
+
+gcc/testsuite/ChangeLog:
+	PR target/104338
+	* gcc.target/riscv/inline-atomics-1.c: New test.
+	* gcc.target/riscv/inline-atomics-2.c: New test.
+	* gcc.target/riscv/inline-atomics-3.c: New test.
+	* gcc.target/riscv/inline-atomics-4.c: New test.
+	* gcc.target/riscv/inline-atomics-5.c: New test.
+	* gcc.target/riscv/inline-atomics-6.c: New test.
+	* gcc.target/riscv/inline-atomics-7.c: New test.
+	* gcc.target/riscv/inline-atomics-8.c: New test.
 
 Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
 ---
  gcc/config/riscv/riscv-protos.h               |   2 +
- gcc/config/riscv/riscv.cc                     |  50 ++
+ gcc/config/riscv/riscv.cc                     |  49 ++
  gcc/config/riscv/riscv.opt                    |   4 +
- gcc/config/riscv/sync.md                      | 318 ++++++++++
- gcc/doc/invoke.texi                           |   8 +
+ gcc/config/riscv/sync.md                      | 301 +++++++++
+ gcc/doc/invoke.texi                           |  10 +-
  .../gcc.target/riscv/inline-atomics-1.c       |  18 +
- .../gcc.target/riscv/inline-atomics-2.c       |  19 +
+ .../gcc.target/riscv/inline-atomics-2.c       |   9 +
  .../gcc.target/riscv/inline-atomics-3.c       | 569 ++++++++++++++++++
  .../gcc.target/riscv/inline-atomics-4.c       | 566 +++++++++++++++++
  .../gcc.target/riscv/inline-atomics-5.c       |  87 +++
@@ -50,7 +59,7 @@ Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
  .../gcc.target/riscv/inline-atomics-7.c       |  69 +++
  .../gcc.target/riscv/inline-atomics-8.c       |  69 +++
  libgcc/config/riscv/atomic.c                  |   2 +
- 14 files changed, 1868 insertions(+)
+ 14 files changed, 1841 insertions(+), 1 deletion(-)
  create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-1.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-2.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-3.c
@@ -61,58 +70,57 @@ Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
  create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-8.c
 
 diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
-index 4611447ddde..0883a6a2e87 100644
+index 5244e8dcbf0..02b33e02020 100644
 --- a/gcc/config/riscv/riscv-protos.h
 +++ b/gcc/config/riscv/riscv-protos.h
-@@ -76,6 +76,8 @@ extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
- extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
- extern bool riscv_gpr_save_operation_p (rtx);
- extern void riscv_reinit (void);
-+extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
-+extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
+@@ -79,6 +79,8 @@ extern void riscv_reinit (void);
  extern poly_uint64 riscv_regmode_natural_size (machine_mode);
  extern bool riscv_v_ext_vector_mode_p (machine_mode);
  extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
++extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
++extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
+ 
+ /* Routines implemented in riscv-c.cc.  */
+ void riscv_cpu_cpp_builtins (cpp_reader *);
 diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
-index 5f542932d13..a5d1562a542 100644
+index e88fa2d6337..694b8c4449e 100644
 --- a/gcc/config/riscv/riscv.cc
 +++ b/gcc/config/riscv/riscv.cc
-@@ -6988,6 +6988,56 @@ riscv_reinit (void)
- #define TARGET_RUN_TARGET_SELFTESTS selftest::riscv_run_selftests
- #endif /* #if CHECKING_P */
+@@ -7143,6 +7143,55 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+ 							& ~zeroed_hardregs);
+ }
  
-+/* Helper function for extracting a subword from memory.  */
++/* Given memory reference MEM, expand code to compute the aligned
++   memory address, shift and mask values and store them into
++   *ALIGNED_MEM, *SHIFT, *MASK and *NOT_MASK.  */
 +
 +void
 +riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask,
 +		       rtx *not_mask)
 +{
-+  /* Align the memory addess to a word.  */
++  /* Align the memory address to a word.  */
 +  rtx addr = force_reg (Pmode, XEXP (mem, 0));
 +
++  rtx addr_mask = gen_int_mode (-4, Pmode);
++
 +  rtx aligned_addr = gen_reg_rtx (Pmode);
-+  emit_move_insn (aligned_addr,  gen_rtx_AND (Pmode, addr,
-+					      gen_int_mode (-4, Pmode)));
++  emit_move_insn (aligned_addr,  gen_rtx_AND (Pmode, addr, addr_mask));
 +
 +  *aligned_mem = change_address (mem, SImode, aligned_addr);
 +
 +  /* Calculate the shift amount.  */
 +  emit_move_insn (*shift, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
-+				      gen_int_mode (3, SImode)));
++				       gen_int_mode (3, SImode)));
 +  emit_move_insn (*shift, gen_rtx_ASHIFT (SImode, *shift,
-+					 gen_int_mode(3, SImode)));
++					  gen_int_mode (3, SImode)));
 +
 +  /* Calculate the mask.  */
-+  int unshifted_mask;
-+  if (GET_MODE (mem) == QImode)
-+    unshifted_mask = 0xFF;
-+  else
-+    unshifted_mask = 0xFFFF;
++  int unshifted_mask = GET_MODE_MASK (GET_MODE (mem));
 +
-+  emit_move_insn (*mask, gen_int_mode(unshifted_mask, SImode));
++  emit_move_insn (*mask, gen_int_mode (unshifted_mask, SImode));
 +
-+  emit_move_insn (*mask, gen_rtx_ASHIFT(SImode, *mask,
-+				       gen_lowpart (QImode, *shift)));
++  emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask,
++					 gen_lowpart (QImode, *shift)));
 +
 +  emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask));
 +}
@@ -121,19 +129,19 @@ index 5f542932d13..a5d1562a542 100644
 +
 +void
 +riscv_lshift_subword (machine_mode mode, rtx value, rtx shift,
-+		     rtx *shifted_value)
++		      rtx *shifted_value)
 +{
 +  rtx value_reg = gen_reg_rtx (SImode);
 +  emit_move_insn (value_reg, simplify_gen_subreg (SImode, value,
 +						  mode, 0));
 +
-+  emit_move_insn(*shifted_value, gen_rtx_ASHIFT(SImode, value_reg,
-+						gen_lowpart (QImode, shift)));
++  emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg,
++						 gen_lowpart (QImode, shift)));
 +}
 +
- /* Implement TARGET_VECTOR_MODE_SUPPORTED_P.  */
- 
- static bool
+ /* Initialize the GCC target structure.  */
+ #undef TARGET_ASM_ALIGNED_HI_OP
+ #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
 diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
 index ff1dd4ddd4f..bc5e63ab3e6 100644
 --- a/gcc/config/riscv/riscv.opt
@@ -147,7 +155,7 @@ index ff1dd4ddd4f..bc5e63ab3e6 100644
 +Target Var(TARGET_INLINE_SUBWORD_ATOMIC) Init(1)
 +Always inline subword atomic operations.
 diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
-index c932ef87b9d..d3acadfa0e0 100644
+index c932ef87b9d..83be6431cb6 100644
 --- a/gcc/config/riscv/sync.md
 +++ b/gcc/config/riscv/sync.md
 @@ -21,8 +21,11 @@
@@ -162,53 +170,10 @@ index c932ef87b9d..d3acadfa0e0 100644
    UNSPEC_ATOMIC_STORE
    UNSPEC_MEMORY_BARRIER
  ])
-@@ -91,6 +94,145 @@
+@@ -91,6 +94,135 @@
    [(set_attr "type" "atomic")
     (set (attr "length") (const_int 8))])
  
-+(define_expand "atomic_fetch_<atomic_optab><mode>"
-+  [(set (match_operand:SHORT 0 "register_operand" "=&r")	      ;; old value at mem
-+	(match_operand:SHORT 1 "memory_operand" "+A"))		      ;; mem location
-+   (set (match_dup 1)
-+	(unspec_volatile:SHORT
-+	  [(any_atomic:SHORT (match_dup 1)
-+		     (match_operand:SHORT 2 "reg_or_0_operand" "rJ")) ;; value for op
-+	   (match_operand:SI 3 "const_int_operand")]		      ;; model
-+	 UNSPEC_SYNC_OLD_OP_SUBWORD))]
-+  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
-+{
-+  /* We have no QImode/HImode atomics, so form a mask, then use
-+     subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
-+     operation. */
-+
-+  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
-+     is disabled */
-+
-+  rtx old = gen_reg_rtx (SImode);
-+  rtx mem = operands[1];
-+  rtx value = operands[2];
-+  rtx aligned_mem = gen_reg_rtx (SImode);
-+  rtx shift = gen_reg_rtx (SImode);
-+  rtx mask = gen_reg_rtx (SImode);
-+  rtx not_mask = gen_reg_rtx (SImode);
-+
-+  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);
-+
-+  rtx shifted_value = gen_reg_rtx (SImode);
-+  riscv_lshift_subword (<MODE>mode, value, shift, &shifted_value);
-+
-+  emit_insn (gen_subword_atomic_fetch_strong_<atomic_optab> (old, aligned_mem,
-+							     shifted_value,
-+							     mask, not_mask));
-+
-+  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
-+					 gen_lowpart (QImode, shift)));
-+
-+  emit_move_insn (operands[0], gen_lowpart (<MODE>mode, old));
-+
-+  DONE;
-+})
-+
 +(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
 +  [(set (match_operand:SI 0 "register_operand" "=&r")		   ;; old value at mem
 +	(match_operand:SI 1 "memory_operand" "+A"))		   ;; mem location
@@ -223,27 +188,22 @@ index c932ef87b9d..d3acadfa0e0 100644
 +    (clobber (match_scratch:SI 6 "=&r"))]			   ;; tmp_2
 +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
 +  {
-+    return
-+    "1:\;"
-+    "lr.w.aq\t%0, %1\;"
-+    "<insn>\t%5, %0, %2\;"
-+    "and\t%5, %5, %3\;"
-+    "and\t%6, %0, %4\;"
-+    "or\t%6, %6, %5\;"
-+    "sc.w.rl\t%5, %6, %1\;"
-+    "bnez\t%5, 1b";
++    return "1:\;"
++	   "lr.w.aq\t%0, %1\;"
++	   "<insn>\t%5, %0, %2\;"
++	   "and\t%5, %5, %3\;"
++	   "and\t%6, %0, %4\;"
++	   "or\t%6, %6, %5\;"
++	   "sc.w.rl\t%5, %6, %1\;"
++	   "bnez\t%5, 1b";
 +  }
 +  [(set (attr "length") (const_int 28))])
 +
 +(define_expand "atomic_fetch_nand<mode>"
-+  [(set (match_operand:SHORT 0 "register_operand" "=&r")
-+	(match_operand:SHORT 1 "memory_operand" "+A"))
-+   (set (match_dup 1)
-+	(unspec_volatile:SHORT
-+	  [(not:SHORT (and:SHORT (match_dup 1)
-+				 (match_operand:SHORT 2 "reg_or_0_operand" "rJ")))
-+	   (match_operand:SI 3 "const_int_operand")] ;; model
-+	 UNSPEC_SYNC_OLD_OP_SUBWORD))]
++  [(match_operand:SHORT 0 "register_operand")			      ;; old value at mem
++   (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand")     ;; mem location
++			 (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op
++   (match_operand:SI 3 "const_int_operand")]			      ;; model
 +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
 +{
 +  /* We have no QImode/HImode atomics, so form a mask, then use
@@ -292,34 +252,69 @@ index c932ef87b9d..d3acadfa0e0 100644
 +    (clobber (match_scratch:SI 6 "=&r"))]				  ;; tmp_2
 +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
 +  {
-+    return
-+    "1:\;"
-+    "lr.w.aq\t%0, %1\;"
-+    "and\t%5, %0, %2\;"
-+    "not\t%5, %5\;"
-+    "and\t%5, %5, %3\;"
-+    "and\t%6, %0, %4\;"
-+    "or\t%6, %6, %5\;"
-+    "sc.w.rl\t%5, %6, %1\;"
-+    "bnez\t%5, 1b";
++    return "1:\;"
++	   "lr.w.aq\t%0, %1\;"
++	   "and\t%5, %0, %2\;"
++	   "not\t%5, %5\;"
++	   "and\t%5, %5, %3\;"
++	   "and\t%6, %0, %4\;"
++	   "or\t%6, %6, %5\;"
++	   "sc.w.rl\t%5, %6, %1\;"
++	   "bnez\t%5, 1b";
 +  }
 +  [(set (attr "length") (const_int 32))])
++
++(define_expand "atomic_fetch_<atomic_optab><mode>"
++  [(match_operand:SHORT 0 "register_operand")			 ;; old value at mem
++   (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand")	 ;; mem location
++		     (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op
++   (match_operand:SI 3 "const_int_operand")]			 ;; model
++  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
++{
++  /* We have no QImode/HImode atomics, so form a mask, then use
++     subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
++     operation. */
++
++  /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
++     is disabled */
++
++  rtx old = gen_reg_rtx (SImode);
++  rtx mem = operands[1];
++  rtx value = operands[2];
++  rtx aligned_mem = gen_reg_rtx (SImode);
++  rtx shift = gen_reg_rtx (SImode);
++  rtx mask = gen_reg_rtx (SImode);
++  rtx not_mask = gen_reg_rtx (SImode);
++
++  riscv_subword_address (mem, &aligned_mem, &shift, &mask, &not_mask);
++
++  rtx shifted_value = gen_reg_rtx (SImode);
++  riscv_lshift_subword (<MODE>mode, value, shift, &shifted_value);
++
++  emit_insn (gen_subword_atomic_fetch_strong_<atomic_optab> (old, aligned_mem,
++							     shifted_value,
++							     mask, not_mask));
++
++  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
++					 gen_lowpart (QImode, shift)));
++
++  emit_move_insn (operands[0], gen_lowpart (<MODE>mode, old));
++
++  DONE;
++})
 +
  (define_insn "atomic_exchange<mode>"
    [(set (match_operand:GPR 0 "register_operand" "=&r")
  	(unspec_volatile:GPR
-@@ -104,6 +246,60 @@
+@@ -104,6 +236,56 @@
    [(set_attr "type" "atomic")
     (set (attr "length") (const_int 8))])
  
 +(define_expand "atomic_exchange<mode>"
-+  [(set (match_operand:SHORT 0 "register_operand" "=&r")
-+	(unspec_volatile:SHORT
-+	  [(match_operand:SHORT 1 "memory_operand" "+A")
-+	   (match_operand:SI 3 "const_int_operand")] ;; model
-+	  UNSPEC_SYNC_EXCHANGE_SUBWORD))
-+   (set (match_dup 1)
-+	(match_operand:SHORT 2 "register_operand" "0"))]
++  [(match_operand:SHORT 0 "register_operand") ;; old value at mem
++   (match_operand:SHORT 1 "memory_operand")   ;; mem location
++   (match_operand:SHORT 2 "register_operand") ;; value
++   (match_operand:SI 3 "const_int_operand")]  ;; model
 +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
 +{
 +  rtx old = gen_reg_rtx (SImode);
@@ -356,32 +351,31 @@ index c932ef87b9d..d3acadfa0e0 100644
 +    (clobber (match_scratch:SI 4 "=&r"))]		 ;; tmp_1
 +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
 +  {
-+    return
-+    "1:\;"
-+    "lr.w.aq\t%0, %1\;"
-+    "and\t%4, %0, %3\;"
-+    "or\t%4, %4, %2\;"
-+    "sc.w.rl\t%4, %4, %1\;"
-+    "bnez\t%4, 1b";
++    return "1:\;"
++	   "lr.w.aq\t%0, %1\;"
++	   "and\t%4, %0, %3\;"
++	   "or\t%4, %4, %2\;"
++	   "sc.w.rl\t%4, %4, %1\;"
++	   "bnez\t%4, 1b";
 +  }
 +  [(set (attr "length") (const_int 20))])
 +
  (define_insn "atomic_cas_value_strong<mode>"
    [(set (match_operand:GPR 0 "register_operand" "=&r")
  	(match_operand:GPR 1 "memory_operand" "+A"))
-@@ -153,6 +349,128 @@
+@@ -153,6 +335,125 @@
    DONE;
  })
  
 +(define_expand "atomic_compare_and_swap<mode>"
-+  [(match_operand:SI 0 "register_operand" "")    ;; bool output
-+   (match_operand:SHORT 1 "register_operand" "") ;; val output
-+   (match_operand:SHORT 2 "memory_operand" "")   ;; memory
-+   (match_operand:SHORT 3 "reg_or_0_operand" "") ;; expected value
-+   (match_operand:SHORT 4 "reg_or_0_operand" "") ;; desired value
-+   (match_operand:SI 5 "const_int_operand" "")   ;; is_weak
-+   (match_operand:SI 6 "const_int_operand" "")   ;; mod_s
-+   (match_operand:SI 7 "const_int_operand" "")]  ;; mod_f
++  [(match_operand:SI 0 "register_operand")    ;; bool output
++   (match_operand:SHORT 1 "register_operand") ;; val output
++   (match_operand:SHORT 2 "memory_operand")   ;; memory
++   (match_operand:SHORT 3 "reg_or_0_operand") ;; expected value
++   (match_operand:SHORT 4 "reg_or_0_operand") ;; desired value
++   (match_operand:SI 5 "const_int_operand")   ;; is_weak
++   (match_operand:SI 6 "const_int_operand")   ;; mod_s
++   (match_operand:SI 7 "const_int_operand")]  ;; mod_f
 +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
 +{
 +  emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
@@ -405,7 +399,7 @@ index c932ef87b9d..d3acadfa0e0 100644
 +    {
 +      rtx difference = gen_rtx_MINUS (SImode, val, exp);
 +      compare = gen_reg_rtx (SImode);
-+      emit_move_insn (compare, difference);
++      emit_move_insn  (compare, difference);
 +    }
 +
 +  if (word_mode != SImode)
@@ -420,15 +414,13 @@ index c932ef87b9d..d3acadfa0e0 100644
 +})
 +
 +(define_expand "atomic_cas_value_strong<mode>"
-+  [(set (match_operand:SHORT 0 "register_operand" "=&r")			;; val output
-+	(match_operand:SHORT 1 "memory_operand" "+A"))				;; memory
-+   (set (match_dup 1)
-+	(unspec_volatile:SHORT [(match_operand:SHORT 2 "reg_or_0_operand" "rJ")	;; expected val
-+				(match_operand:SHORT 3 "reg_or_0_operand" "rJ")	;; desired val
-+				(match_operand:SI 4 "const_int_operand")	;; mod_s
-+				(match_operand:SI 5 "const_int_operand")]	;; mod_f
-+	 UNSPEC_COMPARE_AND_SWAP_SUBWORD))
-+   (clobber (match_scratch:SHORT 6 "=&r"))]
++  [(match_operand:SHORT 0 "register_operand") ;; val output
++   (match_operand:SHORT 1 "memory_operand")   ;; memory
++   (match_operand:SHORT 2 "reg_or_0_operand") ;; expected value
++   (match_operand:SHORT 3 "reg_or_0_operand") ;; desired value
++   (match_operand:SI 4 "const_int_operand")   ;; mod_s
++   (match_operand:SI 5 "const_int_operand")   ;; mod_f
++   (match_scratch:SHORT 6)]
 +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
 +{
 +  /* We have no QImode/HImode atomics, so form a mask, then use
@@ -465,7 +457,7 @@ index c932ef87b9d..d3acadfa0e0 100644
 +  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
 +					 gen_lowpart (QImode, shift)));
 +
-+  emit_move_insn (operands[0], gen_lowpart(<MODE>mode, old));
++  emit_move_insn (operands[0], gen_lowpart (<MODE>mode, old));
 +
 +  DONE;
 +})
@@ -474,24 +466,23 @@ index c932ef87b9d..d3acadfa0e0 100644
 +  [(set (match_operand:SI 0 "register_operand" "=&r")			   ;; old value at mem
 +	(match_operand:SI 1 "memory_operand" "+A"))			   ;; mem location
 +   (set (match_dup 1)
-+	(unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ")  ;; o
-+			     (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; n
++	(unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ")  ;; expected value
++			     (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value
 +	 UNSPEC_COMPARE_AND_SWAP_SUBWORD))
 +	(match_operand:SI 4 "register_operand" "rI")			   ;; mask
 +	(match_operand:SI 5 "register_operand" "rI")			   ;; not_mask
 +	(clobber (match_scratch:SI 6 "=&r"))]				   ;; tmp_1
 +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
 +  {
-+    return
-+    "1:\;"
-+    "lr.w.aq\t%0, %1\;"
-+    "and\t%6, %0, %4\;"
-+    "bne\t%6, %z2, 1f\;"
-+    "and\t%6, %0, %5\;"
-+    "or\t%6, %6, %3\;"
-+    "sc.w.rl\t%6, %6, %1\;"
-+    "bnez\t%6, 1b\;"
-+    "1:";
++    return "1:\;"
++	   "lr.w.aq\t%0, %1\;"
++	   "and\t%6, %0, %4\;"
++	   "bne\t%6, %z2, 1f\;"
++	   "and\t%6, %0, %5\;"
++	   "or\t%6, %6, %3\;"
++	   "sc.w.rl\t%6, %6, %1\;"
++	   "bnez\t%6, 1b\;"
++	   "1:";
 +  }
 +  [(set (attr "length") (const_int 28))])
 +
@@ -499,17 +490,19 @@ index c932ef87b9d..d3acadfa0e0 100644
    [(match_operand:QI 0 "register_operand" "")     ;; bool output
     (match_operand:QI 1 "memory_operand" "+A")    ;; memory
 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
-index a38547f53e5..ce10b24534a 100644
+index a38547f53e5..ba448dcb7ef 100644
 --- a/gcc/doc/invoke.texi
 +++ b/gcc/doc/invoke.texi
-@@ -1216,6 +1216,7 @@ See RS/6000 and PowerPC Options.
- -mpreferred-stack-boundary=@var{num}
- -msmall-data-limit=@var{N-bytes}
- -msave-restore  -mno-save-restore
-+-minline-atomics  -mno-inline-atomics
- -mshorten-memrefs  -mno-shorten-memrefs
- -mstrict-align  -mno-strict-align
- -mcmodel=medlow  -mcmodel=medany
+@@ -1226,7 +1226,8 @@ See RS/6000 and PowerPC Options.
+ -mbig-endian  -mlittle-endian
+ -mstack-protector-guard=@var{guard}  -mstack-protector-guard-reg=@var{reg}
+ -mstack-protector-guard-offset=@var{offset}
+--mcsr-check -mno-csr-check}
++-mcsr-check -mno-csr-check
++-minline-atomics  -mno-inline-atomics}
+ 
+ @emph{RL78 Options}
+ @gccoptlist{-msim  -mmul=none  -mmul=g13  -mmul=g14  -mallregs
 @@ -29006,6 +29007,13 @@ Do or don't use smaller but slower prologue and epilogue code that uses
  library function calls.  The default is to use fast inline prologues and
  epilogues.
@@ -517,9 +510,9 @@ index a38547f53e5..ce10b24534a 100644
 +@opindex minline-atomics
 +@item -minline-atomics
 +@itemx -mno-inline-atomics
-+Do or don't use smaller but slower subword atomic emulation code that
-+uses library function calls.  The default is to use fast inline subword
-+atomics.
++Do or don't use smaller but slower subword atomic emulation code that uses
++libatomic function calls.  The default is to use fast inline subword atomics
++that do not require libatomic.
 +
  @opindex mshorten-memrefs
  @item -mshorten-memrefs
@@ -550,10 +543,10 @@ index 00000000000..5c5623d9b2f
 +}
 diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c
 new file mode 100644
-index 00000000000..fdce7a5d71f
+index 00000000000..01b43908692
 --- /dev/null
 +++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c
-@@ -0,0 +1,19 @@
+@@ -0,0 +1,9 @@
 +/* { dg-do compile } */
 +/* Verify that subword atomics do not generate calls.  */
 +/* { dg-options "-minline-atomics" } */
@@ -562,17 +555,8 @@ index 00000000000..fdce7a5d71f
 +/* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_nand_1" } } */
 +/* { dg-final { scan-assembler-not "\tcall\t__sync_bool_compare_and_swap_1" } } */
 +
-+char foo;
-+char bar;
-+char baz;
-+
-+int
-+main ()
-+{
-+  __sync_fetch_and_add(&foo, 1);
-+  __sync_fetch_and_nand(&bar, 1);
-+  __sync_bool_compare_and_swap (&baz, 1, 2);
-+}
++#include "inline-atomics-1.c"
+\ No newline at end of file
 diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c
 new file mode 100644
 index 00000000000..709f3734377
@@ -2070,5 +2054,5 @@ index 69f53623509..573d163ea04 100644
    type __sync_fetch_and_ ## opname ## _ ## size (type *p, type v)	\
    {									\
 -- 
-2.40.0
+2.35.3