libatomic_ops-7.4.2
OBS-URL: https://build.opensuse.org/package/show/devel:libraries:c_c++/libatomic_ops?expand=0&rev=14
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version https://git-lfs.github.com/spec/v1
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oid sha256:e524cdb5603a66e28127bbd767cc6840e9854b449f7b3bcf6585e0f1391e757b
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size 246464
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libatomic_ops-7.4.2.tar.gz
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libatomic_ops-7.4.2.tar.gz
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version https://git-lfs.github.com/spec/v1
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oid sha256:04fa615f62992547bcbda562260e28b504bc4c06e2f985f267f3ade30304b5dd
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-------------------------------------------------------------------
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Mon Jul 21 08:44:50 UTC 2014 - jengelh@inai.de
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- Update to new upstream release 7.4.2
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* Add and/or/xor entries to list_atomic (tests).
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* Add char/short/int/AO_double_t and dd_acquire cases to list_atomic (tests).
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* Add double_store pthread-based implementation and tests.
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* Add generalized CAS primitives of char/short/int size.
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* Add generalized atomic and/or/xor operations for char/short/int types.
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* Add generalized fetch_and_add_acquire/release (for ARMv6+).
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* Add generic implementation of double_load primitives.
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* Add load/store primitives generalization based on CAS.
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* Add lock-based implementation of char/short/int_fetch_compare_and_swap.
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* Add missing double_compare_and_swap to generalization.
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* Add missing generalization of no-barrier CAS in template.
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* Always use 'mfence' for nop_full if target CPU supports SSE2 (gcc/x86).
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* Cast away volatile on dereference in CAS-based generalization primitives.
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* Define AO_int_X operations for ARM and avr32.
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* Define double-wide ordered loads/stores for x86.
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* Define int_and/or/xor primitives in ao_t_is_int header.
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* Define nop_full as compiler barrier for pre-ARMv6 single-core case.
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* Do not include standard_ao_double_t.h where double-CAS is unimplemented.
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* Do not report absence of meaningless nop, load and store in test_atomic.
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* Eliminate 'missing initializer' warning for AO_stack_t value initializer.
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* Eliminate arithmetic shifts in double-CAS (gcc/arm, msftc/x86).
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* Enable generalization of all variants of CAS via fetch_compare_and_swap.
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* Implement and/or/xor, AO_double_load for ARM.
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* Implement atomic store using direct write by default on ARMv6+.
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* Implement char/short/int-wide primitives using GCC built-in atomic/sync.
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* Implement char/short_fetch_and_add, char/short_load for ARMv6+ (GCC).
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* Implement char/short_store primitives at aligned addresses for ARM.
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* Implement double_load/store based on guaranteed x86 access atomicity.
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* Implement double_store for ARMv7 using LDREXD/STREXD.
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* Implement load/store via simple LDR/STR for ARMv6+ (msftc).
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* Implement nop_full/write using 'dmb' instruction if available (gcc/arm).
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* Minimize gcc/generic-arithm template by factoring out barriers.
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* Move 'unsigned' keyword to XCTYPE in generalize-small template.
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* Move definitions of ordered loads/stores to inner separate headers.
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* Move gcc-generic AO_t-wide primitives to generic-small/arithm headers.
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* Move generalized arithmetical primitives to 'generalize-arithm' template.
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* Optimize AO_spin manually to minimize compiler influence on its duration.
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* Remove X_aligned_atomic_load_store headers and template.
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* Remove duplicate AO_spin and AO_pause definition in atomic_ops_stack.
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* Remove gcc/x86_64.h eliminating code duplication of gcc/x86.h.
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* Remove nested AO_USE_PTHREAD_DEFS macro check in atomic_ops.h (gcc/arm).
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* Remove redundant 'cc' clobber for LDREXD instruction (gcc/arm).
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* Remove store_full from msftc/arm.h in favor of generalized primitive.
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* Reorder AO_double_t union elements for AO_DOUBLE_T_INITIALIZER portability.
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* Replace atomic_load_store.template with atomic_load and atomic_store ones.
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* Support AArch64 (64-bit ARM) target (GCC).
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* Support ARMv8 target (gcc/arm).
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* Use __atomic GCC built-in to implement generic double-wide CAS.
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* Use built-in __sync CAS for double-CAS if AO_USE_SYNC_CAS_BUILTIN for x86.
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- Drop libatomic_ops-aarch64.patch (no longer needed)
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-------------------------------------------------------------------
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Thu May 15 14:53:31 UTC 2014 - tchvatal@suse.com
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Name: libatomic_ops
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Version: 7.2e
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Version: 7.4.2
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Release: 0
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Summary: A portable library for atomic memory operations
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License: GPL-2.0+ and MIT
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Group: Development/Languages/C and C++
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Url: http://www.hpl.hp.com/research/linux/atomic_ops/
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Source: http://www.hpl.hp.com/research/linux/atomic_ops/download/%{name}-%{version}.tar.gz
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Patch1: libatomic_ops-aarch64.patch
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#DL-URL: https://github.com/ivmai/libatomic_ops/wiki/Download
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Source: http://www.ivmaisoft.com/_bin/atomic_ops/libatomic_ops-7.4.2.tar.gz
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Patch2: libatomic_ops-ppc64.patch
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BuildRequires: autoconf
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BuildRequires: automake
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@ -52,8 +53,7 @@ considers memory barrier semantics, and allows the construction of code
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that involves minimum overhead across a variety of architectures.
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%prep
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%setup -q -n %{name}-7.2
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%patch1 -p1
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%setup -q
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%patch2 -p1
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%build
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@ -62,11 +62,10 @@ autoreconf -fvi
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make %{?_smp_mflags}
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%install
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make DESTDIR=%{buildroot} install %{?_smp_mflags}
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%make_install
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rm -f "%buildroot/%_libdir"/*.la
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# remove unnecessary documents
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rm -Rf "%{buildroot}/%{_datadir}/libatomic_ops"
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# fix perms
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chmod 644 doc/*.txt README COPYING AUTHORS ChangeLog
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%check
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%if !0%{?qemu_user_space_build:1}
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@ -75,7 +74,7 @@ make check %{?_smp_mflags}
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%files devel
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%defattr(-,root,root)
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%doc README COPYING AUTHORS ChangeLog
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%doc README.md COPYING AUTHORS ChangeLog
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%doc doc/*.txt
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%{_libdir}/libatomic_ops*.a
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%{_includedir}/atomic_ops/
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