Jan Engelhardt 2014-12-29 15:41:58 +00:00 committed by Git OBS Bridge
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-------------------------------------------------------------------
Mon Jul 21 08:44:50 UTC 2014 - jengelh@inai.de
- Update to new upstream release 7.4.2
* Add and/or/xor entries to list_atomic (tests).
* Add char/short/int/AO_double_t and dd_acquire cases to list_atomic (tests).
* Add double_store pthread-based implementation and tests.
* Add generalized CAS primitives of char/short/int size.
* Add generalized atomic and/or/xor operations for char/short/int types.
* Add generalized fetch_and_add_acquire/release (for ARMv6+).
* Add generic implementation of double_load primitives.
* Add load/store primitives generalization based on CAS.
* Add lock-based implementation of char/short/int_fetch_compare_and_swap.
* Add missing double_compare_and_swap to generalization.
* Add missing generalization of no-barrier CAS in template.
* Always use 'mfence' for nop_full if target CPU supports SSE2 (gcc/x86).
* Cast away volatile on dereference in CAS-based generalization primitives.
* Define AO_int_X operations for ARM and avr32.
* Define double-wide ordered loads/stores for x86.
* Define int_and/or/xor primitives in ao_t_is_int header.
* Define nop_full as compiler barrier for pre-ARMv6 single-core case.
* Do not include standard_ao_double_t.h where double-CAS is unimplemented.
* Do not report absence of meaningless nop, load and store in test_atomic.
* Eliminate 'missing initializer' warning for AO_stack_t value initializer.
* Eliminate arithmetic shifts in double-CAS (gcc/arm, msftc/x86).
* Enable generalization of all variants of CAS via fetch_compare_and_swap.
* Implement and/or/xor, AO_double_load for ARM.
* Implement atomic store using direct write by default on ARMv6+.
* Implement char/short/int-wide primitives using GCC built-in atomic/sync.
* Implement char/short_fetch_and_add, char/short_load for ARMv6+ (GCC).
* Implement char/short_store primitives at aligned addresses for ARM.
* Implement double_load/store based on guaranteed x86 access atomicity.
* Implement double_store for ARMv7 using LDREXD/STREXD.
* Implement load/store via simple LDR/STR for ARMv6+ (msftc).
* Implement nop_full/write using 'dmb' instruction if available (gcc/arm).
* Minimize gcc/generic-arithm template by factoring out barriers.
* Move 'unsigned' keyword to XCTYPE in generalize-small template.
* Move definitions of ordered loads/stores to inner separate headers.
* Move gcc-generic AO_t-wide primitives to generic-small/arithm headers.
* Move generalized arithmetical primitives to 'generalize-arithm' template.
* Optimize AO_spin manually to minimize compiler influence on its duration.
* Remove X_aligned_atomic_load_store headers and template.
* Remove duplicate AO_spin and AO_pause definition in atomic_ops_stack.
* Remove gcc/x86_64.h eliminating code duplication of gcc/x86.h.
* Remove nested AO_USE_PTHREAD_DEFS macro check in atomic_ops.h (gcc/arm).
* Remove redundant 'cc' clobber for LDREXD instruction (gcc/arm).
* Remove store_full from msftc/arm.h in favor of generalized primitive.
* Reorder AO_double_t union elements for AO_DOUBLE_T_INITIALIZER portability.
* Replace atomic_load_store.template with atomic_load and atomic_store ones.
* Support AArch64 (64-bit ARM) target (GCC).
* Support ARMv8 target (gcc/arm).
* Use __atomic GCC built-in to implement generic double-wide CAS.
* Use built-in __sync CAS for double-CAS if AO_USE_SYNC_CAS_BUILTIN for x86.
- Drop libatomic_ops-aarch64.patch (no longer needed)
-------------------------------------------------------------------
Thu May 15 14:53:31 UTC 2014 - tchvatal@suse.com

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Name: libatomic_ops
Version: 7.2e
Version: 7.4.2
Release: 0
Summary: A portable library for atomic memory operations
License: GPL-2.0+ and MIT
Group: Development/Languages/C and C++
Url: http://www.hpl.hp.com/research/linux/atomic_ops/
Source: http://www.hpl.hp.com/research/linux/atomic_ops/download/%{name}-%{version}.tar.gz
Patch1: libatomic_ops-aarch64.patch
#DL-URL: https://github.com/ivmai/libatomic_ops/wiki/Download
Source: http://www.ivmaisoft.com/_bin/atomic_ops/libatomic_ops-7.4.2.tar.gz
Patch2: libatomic_ops-ppc64.patch
BuildRequires: autoconf
BuildRequires: automake
@ -52,8 +53,7 @@ considers memory barrier semantics, and allows the construction of code
that involves minimum overhead across a variety of architectures.
%prep
%setup -q -n %{name}-7.2
%patch1 -p1
%setup -q
%patch2 -p1
%build
@ -62,11 +62,10 @@ autoreconf -fvi
make %{?_smp_mflags}
%install
make DESTDIR=%{buildroot} install %{?_smp_mflags}
%make_install
rm -f "%buildroot/%_libdir"/*.la
# remove unnecessary documents
rm -Rf "%{buildroot}/%{_datadir}/libatomic_ops"
# fix perms
chmod 644 doc/*.txt README COPYING AUTHORS ChangeLog
%check
%if !0%{?qemu_user_space_build:1}
@ -75,7 +74,7 @@ make check %{?_smp_mflags}
%files devel
%defattr(-,root,root)
%doc README COPYING AUTHORS ChangeLog
%doc README.md COPYING AUTHORS ChangeLog
%doc doc/*.txt
%{_libdir}/libatomic_ops*.a
%{_includedir}/atomic_ops/